Help with unloaded ports

Hi everyone,

While running check_design in Genus, I encountered unloaded ports. How can I identify these ports? Does anyone know what might be causing this issue or how it can be resolved?

The design has some unconnected ports left behind by the previous design team, which are causing issues. In certain cases, improperly constrained paths, such as those defined as multicycle or false paths, can also trigger similar warnings.

I do not know this tool, but see similar complaints
for unconnected pins at SRC / ERC in most tools.

Might start with checking "accessory libraries" for
an "open" or "noconn" element, which is there to
satisfy the b!tching for the most part, and attach
it to the port; maybe it quiets down the checker,
maybe it even acts right in terms of reflection and
so on (if Genus is that kind of a tool).