Help With simple DCM VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Counter2_DCM is
    Port ( clk : in  STD_LOGIC;
           reset : in STD_LOGIC;
           clk0 : in  STD_LOGIC;
           clk90 : in  STD_LOGIC;
           DIRECTION0 : in  STD_LOGIC;
           DIRECTION90 : in  STD_LOGIC;
           COUNT_OUT0 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT90 : out  STD_LOGIC_VECTOR (3 downto 0));
end Counter2_DCM;

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architecture Behavioral of Counter2_DCM is

	COMPONENT DCM1
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK90_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;

signal count_int0 : std_logic_vector(3 downto 0) := "0000";
signal count_int90 : std_logic_vector(3 downto 0) := "0000";
signal locked : std_logic;
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begin

	Inst_DCM1: DCM1 PORT MAP(
		CLKIN_IN => clk,
		RST_IN => reset,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => clk0, 
		CLK2X_OUT => open,
		CLK90_OUT => clk90,
		LOCKED_OUT => locked
	);

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process (clk0)

--ERROR:HDLParsers:1411 - "E:/Taylor/FPGA/DMC_counter/Counter1_DCM.vhd" Line 48. Parameter clk0 of mode in can not be associated with a formal port of mode out.

begin
	if clk0='1' and clk0'event then
		if DIRECTION0='1' then
			count_int0 <= count_int0 + 1;
		else
			count_int0 <= count_int0 - 1;
		end if;
	end if;
end process;
COUNT_OUT0 <= count_int0;
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process (clk90)

--ERROR:HDLParsers:1411 - "E:/Taylor/FPGA/DMC_counter/Counter1_DCM.vhd" Line 50. Parameter clk90 of mode in can not be associated with a formal port of mode out.
 
begin
	if clk90='1' and clk90'event then
		if DIRECTION90='1' then
			count_int90 <= count_int90 + 1;
		else
			count_int90 <= count_int90 - 1;
		end if;
	end if;
end process;
COUNT_OUT90 <= count_int90;
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end Behavioral;