Help with output voltage swing

Hi All,

Can someone enlighten me what causing the output voltage swing get clipped shown as circle mark in the diagram? The design is folded cascode op amp with flip voltage follower output stage and Vdd=1.2V. It seems the output voltage range is small. Is this ok in practice?


The schematic is shown in my other post.



Thanks
sj[/url]

sjamil02 said:

The schematic is shown in my other post.

Click to expand...

Could you show the schematic with a DC OPERATING POINT annotation for an input voltage where you get this 400mV VOUT limitation (e.g. for the marked point in the OutputVoltageSwing.pdf)? Perhaps the vdsat sum of PM2 & NM37 then creates this lower limit?

BTW: The inverted (black on white) schematic indeed is very well legible. It would be even better, if you'd remove the grid dots before plotting.

Hi Erikl,

Thanks. Here's the dc operating annotation for vin=200mV and VOUT limited to 300mV. Previously it was 400mV, then I increased the size of output transistors PM2 and PM32 to improve to lower ouput voltage limitation. It's hard to do better than this (<300mV). Any suggestion?

Another thing is, what is the best method to compensate this circuit. I tried placing Cc=7pF at the gate of NM31, for CL=10pF. It seems that it requires Cc almost equal to CL to make the amplifier stable. But this will degrade the bandwidth. I am trying to design a high speed op amp and hence bandwidth is important for me. How to compensate this op amp without degrading the speed too much.

Thanks
SJ

You are using a PMOS for the low side output stage. The output voltage cannot go any lower once it goes into cut-off, ie output below vth.

Thanks checkmate.

Make sense.

How about compensating the op amp. Is it correct to put Cc at the gate of NM31?

sj

sjamil02 said:

Here's the dc operating annotation for vin=200mV and VOUT limited to 300mV. Previously it was 400mV, then I increased the size of output transistors PM2 and PM32 to improve to lower ouput voltage limitation. It's hard to do better than this (<300mV). Any suggestion?

Click to expand...

I think checkmate gave you the right hint.

sjamil02 said:

Another thing is, what is the best method to compensate this circuit. I tried placing Cc=7pF at the gate of NM31, for CL=10pF. It seems that it requires Cc almost equal to CL to make the amplifier stable. But this will degrade the bandwidth. I am trying to design a high speed op amp and hence bandwidth is important for me. How to compensate this op amp without degrading the speed too much.

Click to expand...

Normally, Cc ≈ 20%*CL should be enough, but this is only valid for a Miller compensation cap. Anyway, your Transient Response shows a rather good compromise between speed/bandwidth and ringing. What's your phase margin?

sjamil02 said:

How about compensating the op amp. Is it correct to put Cc at the gate of NM31?
sj

Click to expand...

Correct? Of course!
Efficient? Hell no. The reason why feedback capacitors are often used in miller configuration is that it's effect is multiplied by the gain such that a smaller capacitor can be used. You capacitor should be placed between the output node, and the node with the highest inverting gain from the output node.