Help with optimizing priority-if statements

            STATE_IDLE :
            begin
                // for simplicity, idle state coding will only transit to STATE_ACTIVATE and STATE_REFRESH
                // will implement state transition to STATE_WRITE_LEVELLING and STATE_SELF_REFRESH later
            
                // Rationale behind the priority encoder logic coding below:
                // We can queue (or postpone) up to maximum 8 REFRESH commands inside the RAM.
                // If 8 are queued, there's a high priority request.
                // If 4-7 are queued, there's a low-priority request.
                // If 0-3 are queued, no more are needed (both request signals are false).
                // So READ/WRITE normally go first and refreshes are done while no READ/WRITE are pending,
                // unless there is a danger that the queue underflows,
                // in which case it becomes a high-priority request and READ/WRITE have to wait. 
                // So, in summary, it is to overcome the performance penalty due to refresh lockout at the
                // higher densities
                
                if((refresh_Queue == 0) &&
                   (user_desired_extra_read_or_write_cycles <= MAX_NUM_OF_REFRESH_COMMANDS_POSTPONED))
                begin
                    refresh_Queue <= user_desired_extra_read_or_write_cycles;
                end   


                if ((MPR_ENABLE) ||
                    (extra_read_or_write_cycles_had_passed & high_Priority_Refresh_Request) ||
                    ((user_desired_extra_read_or_write_cycles == 0) & it_is_time_to_do_refresh_now))
                begin
                    // need to do PRECHARGE before REFRESH, see tRP

                    ck_en <= 1;
                    cs_n <= 0;           
                    ras_n <= 0;
                    cas_n <= 1;
                    we_n <= 0;
                    address[A10] <= 0;
                    main_state <= STATE_PRECHARGE;
                    
                    wait_count <= 0;
                end
                
                else if (write_is_enabled | read_is_enabled)
                begin
                    ck_en <= 1;
                    cs_n <= 0;
                    ras_n <= 0;
                    cas_n <= 1;
                    we_n <= 1;
                    
                    bank_address <= i_user_data_address[ADDRESS_BITWIDTH +: BANK_ADDRESS_BITWIDTH];
                        
                    main_state <= STATE_ACTIVATE;
                    
                    wait_count <= 0;
                end
                
                else if (low_Priority_Refresh_Request)
                begin
                    // need to do PRECHARGE before REFRESH, see tRP

                    ck_en <= 1;
                    cs_n <= 0;           
                    ras_n <= 0;
                    cas_n <= 1;
                    we_n <= 0;
                    address[A10] <= 0;
                    main_state <= STATE_PRECHARGE;
                    
                    wait_count <= 0;
                end
                
                else main_state <= STATE_IDLE;
                
            end