Help!! with MUX and Shift Registers in an architecture

[Mai89]

I need some help to implement this architecture please :
assume that (function constant and modular) are implemented
Some notes from the paper i'm working on:
" This is a message scheduler, which uses sixteen shift registers (64-bits). Shift Registers are
loaded with the padded message blocks which require 16-clock cycles. For N rounds of operation, register 15 (R14) is replaced with the result of an equation (I) from message scheduler on the next clock cycle"
If this note is unclear plz ask me.

 

[barry]

EXTREMELY unclear. 16 64-bit registers? You seem to only show 15 registers. What is “equation (I)”? I don’t see that on your drawing. What is BSIZE? What is WSIZE? What is that thing called Wt? What controls the mux? And, most importantly, WHAT IS YOUR QUESTION?

 

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Multiplexer code in VHDL https://www.asic-world.com/examples/vhdl/mux.html
Shift register code in VHDL https://surf-vhdl.com/how-to-implement-a-shift-register-in-vhdl/

 

[Mai89]

EXTREMELY unclear. 16 64-bit registers? You seem to only show 15 registers. What is “equation (I)”? I don’t see that on your drawing. What is BSIZE? What is WSIZE? What is that thing called Wt? What controls the mux? And, most importantly, WHAT IS YOUR QUESTION?

BSIZE= 1024 bit, i divide it to 16 64-bit word and the algorithm contain 80 word one for each round, so words after 15 is generated from word (0:15) using this equation