Help with gate level simulation(how to initial the value during level simulation)

Dear all,

I met the problem when I ran the gate level simulation.

I know exactly reason why did that happen,but no ideal how to fix it up.

The trouble is that the input port of reset is essential in digital circuit design normally. The reset signal will be enabled during chip is power on, then the the inital value of each register will be assigned.

But in my case the reset signal is not available due to specific constraint(The initial state/value of finite state machine/resiger is unknow, but it is not critical during this application.) . Even though without the reset signal, the whole chip needs to function well. It seems that it make sense in real world, but it encounter the problem owe to "unknow value in register in the begginning"during the simulation.

The problem could be fixed up during the RTL simulation by using initial begin to defined the initial condition(settling the value for programming) of each register.

But after logic synthesis(Use design compiler), all the register turn out to be connection with logic gates so could not defined initail condition on connection net. It's not able to simulate like that.

The output waveform is shown below, as you can see the output result of each net is not difine.



I would really appreciate any help.

well you want to initialize all flip-flop, two possibles solutions:
1-
Well, with one backend tool, I reports all flops, and with a tcl script in my simulation tool, I set a random value to each flops.
Take care to mask wrong startup case.
And if your design does not need any reset, you only need to set with random values the main state machine.

2-
with Questa-Mentor tool, the vlog have some attribut to initialize the flop at t=0, I don't if this is applicable to the std-cell flop model. (+initreg)

rca said:

well you want to initialize all flip-flop, two possibles solutions:
1-
Well, with one backend tool, I reports all flops, and with a tcl script in my simulation tool, I set a random value to each flops.
Take care to mask wrong startup case.
And if your design does not need any reset, you only need to set with random values the main state machine.

2-
with Questa-Mentor tool, the vlog have some attribut to initialize the flop at t=0, I don't if this is applicable to the std-cell flop model. (+initreg)

Click to expand...

Thanks a lot.

I have questions about the solution 1, Would you please elaborate that how to set a random value to each flops in tcl script.

How to set the main state machine with random values. Sorry, I am a rookie.

Does the optimized output result of design compiler is affected by the random setting?

best regard,
Joseph

"[expr int(rand()*2)]" returns 0 or 1.