Help with feedback amplifier output range and PMOS sizing in LDO design

[sjamil02]

Hi All,

I attach the schematic (including dc node voltages) for LDO with two-stage OTA and PMOS power device. In order to get dropout voltage of 35mV, I used the following equation to size up the PMOS. W/L=(2Id)/(kp*vdssat2) and vdssat=35mV. I end up with a very huge PMOS, W/L=469153. The regulation voltage Vreg is set based on the following, Vreg=(1+R2/R1)Vref where Vref=0.9V, R2=3.6k and R1=50k. When I put the circuit together and run dc and ac simulation, from ac simulation the gain is below unity. The nmos (x11) of the output stage of an OTA is in triode (vds=59mV). How do I fix this problem? How to size the PMOS to minimize the size while still be able to achieve vdropout=35mV? It seems from my calculation the size is too big!

Please help.

Thks in advance
sj

 

[erikl]

From your sim results, the dropout voltage is 1.5mV @ 50mA, i.e. ron(DC)=30mΩ. For a dropout voltage of 35mV you just need ron(DC)=700mΩ. To be on the safe side, I'd reduce the W/L by a factor of 20 (only).

 

[checkmate]

You would expect the dropout to be minimum when the pass transistor is fully turned on.
Therefore, the dropout is simply iLoad * Rds(on).

You will have to do stability analysis at maximum current load according to specs. That's where compensation is usually required.

 

[dick_freebird]

Your dropout goal sets Rds(on).

Your high-VT process corner and the minimum VIN that you
want to make dropout at, at your minimum VOUT, determine
the "conductance density" per W of the pass FET.

Since you want to be in regulation still, at dropout, you
need some conductance margin beyond that. I would allot
maybe 50% excess worst case conductance, for bad luck
and bad models.

I have had more problems with extremely light load
stability, than full load. Light load makes an output pole
that slides to very low frequency and causes you trouble.
But the output stage gain does drop like a rock as you
bury the pass FET going for low Ron, so your comp
scheme may have to be somewhat adaptive to OP.

 

[sjamil02]

Thanks for the advice. I re-sized my power device using linear equation to get 700mOhm (35mV dropout). Rds(on)=700m=2L/(Kp*W)(VSG-VTH) and after few tweaking I end up with L=0.3um and W= 6004um (Not so big compared to my first design ). The problem now is since the PMOS has to be in triode, its gate voltage is very close to gnd i.e. Vgate=35mV and VSG=1V. (see schematic). The output of the feedback amplifier swing close to gnd and nmos (x11) in triode and hence the amplifier gain drop below unity. If I understand it correctly, the feedback amplifier's output range need to be able to swing close to gnd while still operate in saturation? What is suitable topology to remedy this problem? Class AB output stage? Or is there any simple solution to my problem described here?

Please help

 

[erikl]

Just a question: Why do you feed back only 6.7% of your output voltage, and not 90%, which would match with your ref. voltage? You loose a lot of valuable gain by this!

 

[sjamil02]

Hi Erikl,

Why do you feed back only 6.7% of your output voltage, and not 90%, which would match with your ref. voltage? You loose a lot of valuable gain by this!

Can you explain little bit more on this?

I used the following equation to set my Vreg. (Please correct me if i'm wrong!). Vreg=(1+R2/R1)Vref and I set Vref=900mV and thus R1=3.6k and r2=50k. This is how I end up with only 6.7% of my output voltage.
Should I feedback 90% of output voltage instead?

Please suggest correct method of setting the feedback to obtain the regulation voltage.

Thks
sj

 

[erikl]

Vreg=(1+R2/R1)Vref

No: Vreg=(1+R1/R2)Vref

Should I feedback 90% of output voltage instead?

Of course! The feed-back voltage must be equivalent to your ref. voltage.

 

[sjamil02]

Thanks Erikl for correcting me.

Now I managed to get the regulation level and the regulator is stable @light load=1mA and also heavy load=50mA. As you can see from the attached loop gain sim results, @IL=50mA, Fu=250kHz, Phase=52Deg, Gain=50dB AND @IL=1mA, Fu=2MHz, Phase=69Deg, Gain=65dB. When I run transient sim (see attachment), the VREG bounce (from IL=1mA-->50mA) is quite huge (~ 750mV). What causing this? How to make the vreg bounce smaller? Should I further stabilize the LDO to make the phase margin especially at heavy load (increase phase >65deg?).

 

[erikl]

... the regulator is stable @light load=1mA and also heavy load=50mA. As you can see from the attached loop gain sim results, @IL=50mA, Fu=250kHz, Phase=52Deg, Gain=50dB AND @IL=1mA, Fu=2MHz, Phase=69Deg, Gain=65dB.

Not bad at all! Congratulations!

When I run transient sim (see attachment), the VREG bounce (from IL=1mA-->50mA) is quite huge (~ 750mV). What causing this? How to make the vreg bounce smaller? Should I further stabilize the LDO to make the phase margin especially at heavy load (increase phase >65deg?).

You may try, but I doubt it. Or try a load-dependent phase compensation.
The powerMOS driver stage may be is a bit weak (it has to drive a huge gate load, after all), you could try and enlarge it, especially the nmos (x11).
If all this doesn't help, increasing your external load cap (C14) will decrease the big bounce.
Good luck! erikl

 

[sjamil02]

Cool. Thanks it really help

 

[pegasus97]

Guys, I have to say your comments really helped me .. Thank you so much