Rocketmagnet
Junior Member level 3
Hi all,
I'm trying to design a DCDC regulator with the LTC3810 from Linear. It seems to be a great little chip, but there's one part of the design that's slightly out of my league:
Loop compensation...
According to the datasheet, I need to generate a bode plot of the behaviour of the system, and from that I can calculate the required loop compensation components. According to the datasheet, I fill in the component values into this SPICE code:
Then plot the Gain and Phase of v(out)/v(ith). However, when I do this, the Gain curve looks OK, but the Phase looks nothing like the example one on the datasheet. For a start, it seems to be upside down, so I plotted v(ith)/v(out) which now seems to be the right way up.
But, no matter how I fiddle the values in the SPICE code, I cannot get it to look much like the example graph from the datasheet. I.E. most of the Phase curve is greater than -90. In mine, all of the Phase curve is less than -90.
Can anyone sort me out? Many thanks in advance.
Hugo Elias - Shadow Robot Co Ltd
P.S. the other thing that seems to be strange is that there's no value for output inductance in the SPICE code!
I'm trying to design a DCDC regulator with the LTC3810 from Linear. It seems to be a great little chip, but there's one part of the design that's slightly out of my league:
Loop compensation...
According to the datasheet, I need to generate a bode plot of the behaviour of the system, and from that I can calculate the required loop compensation components. According to the datasheet, I fill in the component values into this SPICE code:
Code:
*3810 modulator gain/phase
*2006 Linear Technology
*this file simulates a simplified model of
*the LTC3810 for generating a v(out)/v(ith)
*bode plot
.param rdson=.0135 ;MOSFET rdson
.param Vrng=2 ;use 1.4 for INTVCC and 0.7 for ground
.param vsnsmax={0.173*Vrng-0.026}
.param Imax={vsnsmax/rdson}
.param DL=4 ;inductor ripple current
*inductor current
gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2}
*output cap
cout out out2 270u ;capacitor value
resr out2 0 0.018 ;capacitor ESR
*load
Rout out 0 2 ;load resistor
vstim ith 0 0 ac 1 ;ac stimulus
.ac dec 100 100 10meg
.probe
.endThen plot the Gain and Phase of v(out)/v(ith). However, when I do this, the Gain curve looks OK, but the Phase looks nothing like the example one on the datasheet. For a start, it seems to be upside down, so I plotted v(ith)/v(out) which now seems to be the right way up.
But, no matter how I fiddle the values in the SPICE code, I cannot get it to look much like the example graph from the datasheet. I.E. most of the Phase curve is greater than -90. In mine, all of the Phase curve is less than -90.
Can anyone sort me out? Many thanks in advance.
Hugo Elias - Shadow Robot Co Ltd
P.S. the other thing that seems to be strange is that there's no value for output inductance in the SPICE code!