HELP With AD9834 Please!!

[wood_girl]

hi, i really appreciate your help, i have been working with an AD9834, it´s work fine at low frecuencies, but at highs the nominal 600mV start to fall. therefore at 30MHz the signal its only 70mV without any filter, i dont know what is the problem, maybe the capacitors?, the PCB?, the firmware??. any idea??...

the MCLK its 75Mhz
the control was made with a 18f2550 and SPI interface
the R is 6,8K
I removed form the PCB the extra capacitors of 0,1uF and the filter and the problem is the same...

pd: sorry for my bad english!!

 

[zorx]

Look at this document:

"Fundamentals of Direct Digital Synthesis (DDS)"
https://www.analog.com/static/imported-files/tutorials/MT-085.pdf

On the page 5, Figure 5, you will see that the amplitude response of the DAC output follows a sin(x)/x response. This is in the "nature" of DDS output, so the closer you are to Fclk/2 (which in your case is 75MHz/2=37,5MHz), the lower the amplitude is going to be.

This can be compensate with antialiasing filter that will have transfer function ~x/sin(x) in the range of interest.

Because of this, and higher order harmonics that fold back in the baseband, some manufacturers recommend that DDS should be chosen so that maximum desired frequency is less or equal than 35% of master clock frequency. From my experience, it all depends on the application. This week I'll test my AD9834 board, and let you know the results.

 

[wood_girl]

thanks for the answer zorx, im going to take a look at de .PDF document.....

im just realized that ihave a AD9834 BRUZ, this ref works with a MCLK of 50MHz, and I have a 75Mhz MCLK (this is for the CRUZ REF) maybe this can be a big issue too, what do you think??..

i hope you can tell me how your results with your ad9834!!!

regards

W_G

 

[zorx]

Hello again, and sorry for a little late feedback.

I still haven't resolved all my issues with DDS, but I'll tell you my observations so far.

First of all, DDS output signal of frequency of Fmclk/2, where Fmclk is master clock of the DDS, is very tricky.
Why?
Because, for generating signal of Fmclk/2 frequency, DDS reads from the sin lookup table only two samples - one from positive and one from negative part. In case of AD9834 there are overall of 2^12=4096 samples in lookup table. So, which two samples are taken? If you follow the startup procedure from datasheet (power up, RESET = high, program the registers, RESET = low), then the 1. sample is taken, and after that sample number 2048 (that represents the phase of 180 degrees). But the problem is that those two samples are of zero value (sin(0) = 0 and sin(180)=0). And the amplitude of the output signal is 0 (or very, very small). So, after the power up and programming, you have to write value of 1023 (that represents phase of 90 degrees) to the phase register, so the output signal is of maximum amplitude (the two samples from lookup table in this case are sin(90)=1 and sin(270)=-1). I think that Analog Devices later introduced COS lookup table so that in case of Fmclk/2 no phase shift at the beginning is needed.
Second thing, in one of the application notes that describes the synchronization of multiple DDS chips, is mentioned that, in case of frequency hopping (when DDS changes frequency from FREQ0 to FERQ1 and viceversa), this process is not phase coherent - that means that if you switch from FERQ0 = Fmclk/2 to lets say FREQ1=Fmclk/10, and then go back to FERQ0, signal with FERQ0 won't have the same phase as before switching to FERQ1. The problem in this case is that, when switch back to FERQ0, any amplitude can happend - from zero to maximum, and you don't have control over this. This can be easily checked if you change from FERQ0 to FERQ1 and back (lets say every 2s), you will notice that amplitude of signal with frequency FERQ0=Fmclk/2 is different every time.
So, in your case, when output amplitude of signal of Fmclk/2 frequency is too small, try to write some value from 0 to 1023 in 12-bit phase register, and you will get the maximum possible amplitude. Also, any other frequency less than Fmclk/2 will not produce this problem (not so obviously).
I strongly suggest you to read the datasheet of AD9834, especially the part about the powering up procedure on the page 17.

Hope this will help a little

Regards

P.S. If I notice something else important, I'll let you know.

----------------------------------------------------------------------

I forgot, regarding the DDS that you're using (50MHz maximum Fmclk) - it sure affects performance if you make it work on 75MHz. But, I tried my DDS (with 75MHz max Fmclk) on 120MHz, and I have generated the signals of 50MHz without any problem. But I don't advise you to do those kind of things. Maximum absolute ratings in the datasheets should be respected, or damage can occur.

-----------------------------------------------------------------------

Another important thing - the schematic of the evaluation board has an error. The capacitor that you mentioned (0,1uF at the output) is also drawn in the schematics, and should be removed or placed one with very small value. I also had the same problem with small amplitudes after 10kHz !!! But everything was fine when I removed it.

 

[wood_girl]

hey zorx!!, im late for this reply!, but ihave been very busy trying to make a new board for my 46.6Mhz MCLK and DDS and the op amp part (to make a 3vp-p signal), until now it´s a mess, no possitive results.. but im still fighting jejeje..... nothing to say for now, and how you doing with your DDS??

 

[wood_girl]

mmmm... bad news, the problem wasn´t the 75MHZ MCLK, the proble remains, and i have send a 90 phase value, but nothing happend, i need to mantain de amplitude at 600mV at least at 10MHZ, cry cry!!...

 

[zorx]

Ok, can you tell me what are the values of the Fmclk, Rset, Rload, and Vsupply? And what are the frequencies that you need to generate?

Saludos

 

[wood_girl]

OMG!!! do you speak spanish!!???...

well im from colombia and i write spanish so much better than english so...

mira la Fmclk la cambie de 75Mhz a 46.666Mhz, ese es el cristal que trabajo ahora, la Rset es de 6.8K Omhios, Rload de 220 , y para Vsupply solo manejo la fuente del USB de mi PC, y con estos valores necesito generar frecuencias hasta 18Mhz por ke entiendo que para el cristal con el que trabajo ahora seria mas o menos la maxima frecuencia que puedo conseguir, pero aun asi se atenua demasiado.


te adjunto unas imagenes de las señales de salida, sin ningun filtro conectado

por otro lado contacte a Analog y esto fue lo que me dijeron: Try unloading the part and checking if the amplitude varies with frequency –dissconnect R8 from IOUTB. Have you checked the MCLK to make sure it acts correctly ? See expected results in attached plots.

ahi te adjunto esas grafiquitas por que yo no las entendi muy bn que digamos, gracias por tu ayuda

 

[wood_girl]

hi zorx, i have been doing everything, but the signal still dropps, maybe is the TH resistors connected to IOUTB, im going to change it to SMD resistors...

one question, do yo have de 600mV at high frecuencies, or do you have the same problem that me??.


regards

W.G

 

[zorx]

Hi,

Sorry, I didn't have time to look at your documents that you attached in the previous message. I'll look during the weekend and let you know.
I've tested my DDS board on 46,6MHz and generated signals of different frequencies. Only on a very low frequencies (10KHz) I got on the output around 590mV Peak-to-Peak. At the higher frequencies the amplitude goes down (if you looked at the document that I was talking about). On the Fmclk/2 you will get 3,92dB lower signal which gives you 600mV/(10exp(0.392))=240mV. So it is normal and you can not maintain 600mV on higher frequencies. I think that with Fmclk=46,6MHz, I got signal with F=Fmclk/2 around 170mV Peak-to-Peak. On Monday I'll tell you the values that I measured for the different frequencies.

Saludos

 

[wood_girl]

hi, i undersatand what you say, but since 1MHZ attenuation starts??? if this is true, this DDS sucks!! LOL, sorry im a llttle frustrated.... i´ll wait for the results on monday, thanks a lot zorx!

 

[zorx]

Hola,


Ok, this is what I measured:
======================================
Rset=6k8, Rload = 200, Vcc = 3,3V, Fmclk=72MHz:
-----------------------------------------------------------------
1) Fout=10Hz => Vp-p=570mV (from 40mV to 610mV)
2) Fout=10kHz => Vp-p=370mV (from 140mV to 510mV)
3) Fout=1MHz => Vp-p=340mV (from 150mV to 490mV)
4) Fout=10MHz => Vp-p=260mV (from 200mV to 460mV)
======================================

Fmclk=46,6MHz:
-----------------------------------------------------------------
1) Fout=10MHz => Vp-p=260mV (from 200mV to 460mV)
======================================


So, my results are similar to those that you got on the pictures you attached. I don't quite understand the diagrams that you received from Analog Devices.

So, regarding your disappointment about DDS, I think that you can not do much better than this. You can go to the configuration page of AD9834 on Analog.com at address
**broken link removed**
and try with different values. You can try to lower the Rset to achive higher output, but the maximum of Vout=Iout*Rload can not exceed 0,8V.
This is just it, not only for this DDS but for the others, too. Unless they have some amplifier built-in. Usually, DDS is used in some PLL circuitry, so output signal is not directly from DDS.

Or, maybe we are both doing something wrong.

Another thing about DDS, in general. I tested 2 DDS chips that work synchronously and I wanted to generate two signals with the same frequency of F1=F2=Fmclk/2, and to control the phase shift beetwen those two signals. In this case that can not be done, because of the "Fmclk/2 thing". I wanted to sweep the phase difference, but the only thing is that the signal, which phase is changed, is decreasing in amplitude (for the phase2 from 0 to 180) but still in phase with first signal, and then they are in counterphase (for the phase2 from 180 to 360).

Crazy thing.

Ok, now I'll tell you what else I did, but I do not recommend this to anyone.
Since I was driving the Fmclk input of DDS with one signal generator, I could increase the Fmclk. So I tried with Fmclk = 100MHz, and it worked. Then I tried with Fmclk = 150MHz, and it worked. Then I tried with Fmclk = 250MHz, and it worked. It worked up to Fmclk = 400MHz, and then I had to increase power level of clock signal. Funny thing is that DDS chip was still pretty cool (of course with increased consumption).
So, you can eventually increase Fmclk beyond 75MHz and thus increase amplitude on 10MHz (but I still don't recommend this).

Salud

 

[wood_girl]

thats a funny thing, since an application eng. from AD says that the amplitud should be the same until FMCLK/2... im getting crazy about this...

i have been thinking in develop a sistem for change the RSet depending on the frecuency output.. i dont know.. maybe can be a solution. or an AGC.... what do you think, it could work huh???....


regards

jenn

 

[zorx]

Playing with Rset is one option. Equivalently, you can change the voltage on the other side of Rset. Look at this article:

"DDS device provides amplitude modulation"
**broken link removed**

But, what if you put an operational amplifier on the output of the DDS with enough amplification that will increase enough the smallest amplitude (the big ones will be clipped) but after that you can put a R-C or L-C filter on the output of operational amplifier, and you will get the sine signal?
A quick look at the Analog.com, and I found this opamp:

"OP162: 15 MHZ RAIL-TO-RAIL OPERATIONAL AMPLIFIER, SINGLE"
https://www.analog.com/en/amplifier...mplifiers-op-amps/op162/products/product.html

But you can check for another one that will suit your needs.

Also, look at this article (not directly related to your problem):

"DDS applications"
**broken link removed**


Saludos

 

[wood_girl]

hey zorx, i have news, i found an RF signal Generator (CRG-450B from GW winstek) with a frecuenci range of 100Khz - 150MHz, and guess what, its the same output, the signal attenuates exactly the same, therefore, there is a problem with the oscilloscope or the leads, im still looking for that problem, thanks for the articles im going to read them.

 

[saurabh17g]

i m also planning to do the generation of 0Hz to 10MHz frequency using AD9834. will u plz give me working PCB diagram

 

[bracelet5460]

nice discussing with AD9834,
the problem i have met:
1 condition:
ad9834 is controlled by ATmega16 (MCU) with SPI interface, the rate is 500KHz, SCK is high when idle, and sampling data in falling edge. DVDD and AVDD are applied with the same voltage +5VDC, Rset=6.8K,Rload=330, and the capacitances are the similiar with the ad9834 evaluated board.
the initial sequence for ad9834 is 2100 50C7 4000 C000 2000.
2. problem
it didn't talk to each other, and i have used oscilloscope and find the data is settled before the SCK falling edge arrives. but the waveform of Iout is changed variously both frequency or amplitude.
i just wonder the initial sequence of AD9834?
and tomorrow i will try to change the initial sequence in two ways:
1), 2100 50C7 4000 8000 8000 C000 C000 E000 2000
2), 2100 2000 50c7 4000
and i will updated for the news.
hopely to discuss with u, my friends,
my email:bracelet5460@yahoo.com.cn

Hola,



Ok, this is what I measured:
======================================
Rset=6k8, Rload = 200, Vcc = 3,3V, Fmclk=72MHz:
-----------------------------------------------------------------
1) Fout=10Hz => Vp-p=570mV (from 40mV to 610mV)
2) Fout=10kHz => Vp-p=370mV (from 140mV to 510mV)
3) Fout=1MHz => Vp-p=340mV (from 150mV to 490mV)
4) Fout=10MHz => Vp-p=260mV (from 200mV to 460mV)
======================================

Fmclk=46,6MHz:
-----------------------------------------------------------------
1) Fout=10MHz => Vp-p=260mV (from 200mV to 460mV)
======================================


So, my results are similar to those that you got on the pictures you attached. I don't quite understand the diagrams that you received from Analog Devices.

So, regarding your disappointment about DDS, I think that you can not do much better than this. You can go to the configuration page of AD9834 on Analog.com at address
**broken link removed**
and try with different values. You can try to lower the Rset to achive higher output, but the maximum of Vout=Iout*Rload can not exceed 0,8V.
This is just it, not only for this DDS but for the others, too. Unless they have some amplifier built-in. Usually, DDS is used in some PLL circuitry, so output signal is not directly from DDS.

Or, maybe we are both doing something wrong.

Another thing about DDS, in general. I tested 2 DDS chips that work synchronously and I wanted to generate two signals with the same frequency of F1=F2=Fmclk/2, and to control the phase shift beetwen those two signals. In this case that can not be done, because of the "Fmclk/2 thing". I wanted to sweep the phase difference, but the only thing is that the signal, which phase is changed, is decreasing in amplitude (for the phase2 from 0 to 180) but still in phase with first signal, and then they are in counterphase (for the phase2 from 180 to 360).

Crazy thing.

Ok, now I'll tell you what else I did, but I do not recommend this to anyone.
Since I was driving the Fmclk input of DDS with one signal generator, I could increase the Fmclk. So I tried with Fmclk = 100MHz, and it worked. Then I tried with Fmclk = 150MHz, and it worked. Then I tried with Fmclk = 250MHz, and it worked. It worked up to Fmclk = 400MHz, and then I had to increase power level of clock signal. Funny thing is that DDS chip was still pretty cool (of course with increased consumption).
So, you can eventually increase Fmclk beyond 75MHz and thus increase amplitude on 10MHz (but I still don't recommend this).

Salud