help--why pll ck_out is quitely lower than design purpose?

[fencl]

after tape out, one chip's pll is 'out of work' sometimes.
for eg. fin=35M/s, fout=280M/s,my pll is simple with pd,chp,vco,and 1/8 devider for comparation with fin, even without lock check circuit. I can test ck_out by 1/4 divider. that is 70M/s, sometimes it is well meet, sometimes it will go to 60M/s. each times i power up, 90% will be 60M/s,10% will be 70M/s.and only one chip in many chips have this problem.
i use some way connect this bad chip fin to other pll for input ,it's work well. and other chip fin to this pll for input.still the same bad case.
what problem is it ? need help sincerely!

 

[mmic1978]

Re: help--why pll ck_out is quitely lower than design purpos

be careful the VCO output driver capability

Frequency output change, maybe you can debug like these ways:

1. VDD pulling, please confirm the voltage supply;

2. PLL locking, if you PLL not get locked well, or loop PM not enough, the output frequency also change;

3. Load pushing: the test div-4 is build in the PLL loop, or open loop divder? please use a perfect RF proble to test

4. div-8, if it work unnorm, you can let the VDD 10% higher to test

5. your PLL loop work badly (LPF is simple 2-order) also can get large jitter

try and debug, blesh you~~

 

[fencl]

Re: help--why pll ck_out is quitely lower than design purpos

Thanks mmic1978,at last we find the problem,it's just the power supply issues as you said.
the power supply chip on PCB vary with current. means vout=vdd vary in large range. this happened with poor dirvering.

be careful the VCO output driver capability

Frequency output change, maybe you can debug like these ways:

1. VDD pulling, please confirm the voltage supply;

2. PLL locking, if you PLL not get locked well, or loop PM not enough, the output frequency also change;

3. Load pushing: the test div-4 is build in the PLL loop, or open loop divder? please use a perfect RF proble to test

4. div-8, if it work unnorm, you can let the VDD 10% higher to test

5. your PLL loop work badly (LPF is simple 2-order) also can get large jitter

try and debug, blesh you~~