Help: VIA antenna error in layout

[xjtulw]

hi, I'm doing antenna drc check for my circuit layout by using tsmc 90nm PDK.
There are a lot of VIA antenna drc errors in my check summary file.
here is the detailed information:

A.R.4.VIA2 { @ (VIA2 area / gate area) > 20
NET AREA RATIO VIA2 GATE_VIA M2_DIO > 20 ...

Did anyone here ever have similiar errors?

Please give me any hints or ideas on it.

Thanks a lot!

Best Regards,

 

[dick_freebird]

Find the net with the vias, break it and jumper with a higher
level metal strap (and appropriate VIAx). That way the VIA2
(or some of them) will not be connected until later and "don't
count".

 

[jgk2004]

The antenna rule is due to the manufacturing process. When making the IC if the lines are too long they build up charge and can blow. Thus you should have long traces jump from one met level to the next or back down like freebird said. This will remove the errors

 

[xjtulw]

Thanks, freebird and jgk2004. I've already figured it out.
It seems that antenna diodes and jumper are very effective in dealing with such errors.