jcpu
Full Member level 4
![Full Member level 4](/styles/images/ranks/flevel1.gif)
Hi! Need some help here, a commonly deployed CMFB circuitry:
where clock rate is 1MHz.
1 & 2 denotate two non-overlaped clock phase;
0.5p & 1p stands for capacitors;
My apology if this circuit still looks awkward,
I shall learn to post the circuit in GIF format.
And I need continuous time equivalent circuit for .noise simulation.
Thanks in advance!
Code:
Vo+ ------/ ---------/ ------- Vcmref
| 1 | 2
| |
| |
1p=== ===0.5p
| |
| |
Vcmfb ------/ ---------/ ------- Vbias
| 1 | 2
| |
1p=== ===0.5p
| |
| |
Vo- ------/ ---------/ ------- Vcmref
1 2
1 & 2 denotate two non-overlaped clock phase;
0.5p & 1p stands for capacitors;
My apology if this circuit still looks awkward,
I shall learn to post the circuit in GIF format.
And I need continuous time equivalent circuit for .noise simulation.
Thanks in advance!