bsprajc
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Hi I'm trying to understand how the DMA ACK and DMA RQ signals are supposed to operate durning a multi word DMA transfer on an IDE ATA Drive or Compact Flash.
My understanding is that after the read command is written to the drive,
the drive will assert DMA RQ, then the host will assert DMA ACK.
After a few cycles,the drive should post the read data and while this is going on, the drive will toggle DMA RQ for each word of data, and while this is happening, DMA ACK will remain asserted (no toggle) until the transfer is complete, and when complete the host will de-assert the DMA ACK line.
Can anyone confirm if my understanding is correct?
Thanks
Barry
My understanding is that after the read command is written to the drive,
the drive will assert DMA RQ, then the host will assert DMA ACK.
After a few cycles,the drive should post the read data and while this is going on, the drive will toggle DMA RQ for each word of data, and while this is happening, DMA ACK will remain asserted (no toggle) until the transfer is complete, and when complete the host will de-assert the DMA ACK line.
Can anyone confirm if my understanding is correct?
Thanks
Barry