Help to understand about a description in a CDR paper

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prcken

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please help to see the attached picture. in the highlighted part, what is "single, multi-bit" ?

is there anyone did this kind of high-speed dual-loop digital CDR before?

Thanks!

 

The output of a single phase detector is a one-bit signal. The author intends to take several phase detectors which produce one-bit signals and add their outputs, resulting in a single signal which has multiple bits. For example, if there are eight phase detectors which all have 1-bit outputs, the result is a single 3-bit signal whose value is simply the binary sum of the phase detectors' outputs. The author described this operation as "boxcar filtering" and "decimation," but it's much simpler than that.
 
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    prcken

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thanks! the word single and multi confused me.
seems more clear to me now. it looks like working as a decimal to binary encoder?
 

it looks like working as a decimal to binary encoder?
Click to expand...

Not quite. It is performing a summing function. In sequential logic, this might be a counter which counts the OR'ed phase detector pulses; in combinational logic, this could be implemented as multiple stages of adders--in this example, 3 stages.
 

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