help to synthesize these verilog circuits.

[triquent]

1)what kind of circuits will be synthesized into?
module aa(ck, r1, r2)
input ck;
output r1, r2; reg r1, r2;
always @(posedge ck) begin
r1<=r2;
r2<=r1;
end
endmodule
2)waht kind of combinational circuits will be sythesized into?
module bb(a, b, x)
input a, b;
output x; reg x;
always@(a or b)begin
x=func(a,b);
end
function func;
input a, b;
if (a)
func=b;
endfunction
endmodule

for 3) and 4) are they going to be synthesized into the same circuits? what kind of circuits will they be synthesized into?
3)always@(d or r1 or r2) begin
r1=d;
r2=r1;
end
4)always@(d or r1 or r2) begin
r2=r1;
r1=d;
end

Which book is good for learning the synthesis?

 

[eziggurat]

The first one is two flip-flops where the one of the flip-flop output is connected to the second flip-flop input and vice versa. I have never used a flip-flop in this way and problems of unknown states as the input is not initialised.

The second one seem to be wrong with func=b.

I am sure you can work the others out.

Search the internet for verilog tutorial.

 

[haoboy]

the best way is to design a simple circuit,and then use DC,from the problems ,u can get more.

 

[nj_jack]

you had better design it with sch. it is easy to understand.