Hi All
I need some information about system verilog. Please help me in this regard
1) Is system verilog used widely?
2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog?
3)which tools support system verilog?Do NC-verilog support it?Are there any special command other than common ones in a tool to simulate system verilog?
4)Is it features both synthesizable and simulation specific constructs?
5)How can learn system verilog ?
6)How does it fit with VHDL,system C,Vera and Specman?
Adoption is increasing, since SV is a large language, it will be hard to measure this. AFAIK, lot of people started using/showing interest in SV. Read deepchip.com, verificationguild.com etc. for more staistics.
2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog?
Yes, it is 100% backward compatible. Infact SV LRM is over and above V2K LRM.
3)which tools support system verilog?Do NC-verilog support it?Are there any special command other than common ones in a tool to simulate system verilog?
I know VCS does it a lot. Mentor's Questa, NC etc. also support. From what I read on web, NC seems to be little behind. I believe you need a switch such as -sv31a or some thing like that - read their manual.
4)Is it features both synthesizable and simulation specific constructs?