Help Required In I2C Protocol

[sakthikumaran87]

Hi All,

I have started my career as VLSI Design Engineer and i am trying hard to learn certain things in synthesis and STA. I have created an I2C Slave with the intention that it should support std, fast and HS mode. I have completed coding it in Verilog HDL and have made sanity verification. Now on coming to synthesis part, i went through the SDC constraints and found that the commonly used SDC commands by the front end designer are: create_clock, set_input_delay, set_output_delay, set_max_tran, set_driving_cell, set_max_capacitance, set_max_fanout etc.,

My doubts are:

1. The design intention is to make the slave work with internal clock frequency of 34MHz. when i went through the protocol i went through pages consisting of various values in a table, so called as characteristic table. I don't know how to relate them with the aforesaid SDC commands.
2. I have read that set_i/o_delay is the time we give for the inputs to reach the DUT/ to go out of the DUT. If i am not sure of what is the block that drives my input in real environment then what is the assumption i have to make for this value.
3. How to set max_trans value. I read that its the input slew value and all the inputs should have less than or equal to this slew value. if it is the case how to decide what is the required slew value for my design? will it be specified in the technology liberty file or will be given in spec?
4.How to decide on max_cap_value,max_fanout and driving_cell?

i think i am lagging in these aspects and will be thankful if any one of you can guide ma in this regard.

Thanks in advance.

Sk

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Hi,

Also kindly let me know the other important commands that i have missed out and the ways to find out the values/assumptions for them.

Thanks in advance,

Sk

 

[yx.yang]

Hi, sakthikumaran87:
It seem you are looking into it, but there does a long way to go.
"2. I have read that set_i/o_delay is the time we give for the inputs to reach the DUT/ to go out of the DUT. If i am not sure of what is the block that drives my input in real environment then what is the assumption i have to make for this value." For this: there maybe following situations:
2.1): The protocal itself defined the input/ouptut delay of the source chip and destination chip clearly. For example: the PCI specification defined this well. So all the chip will meet the timing spec and when they connected up to make a system, there will be no problem.
2.2): The external chip must have input/output delay specification in its document. You can get these values from doc of the chip you will connected to. Such as DDR memory.

"3. How to set max_trans value. I read that its the input slew value and all the inputs should have less than or equal to this slew value. if it is the case how to decide what is the required slew value for my design? will it be specified in the technology liberty file or will be given in spec?" For this: the technical library (*.lib) will define this. You usually don't need to change them for your internal cells. While for your chip Input/Output related cells, you do need do the following:
3.1): for chip inputs: use set_input_transition and set_input_delay to constraint them.
3.2): for chip outputs: use set_max_transiton/set_output_delay/set_output_load to constraint them.
"4: How to decide on max_cap_value,max_fanout and driving_cell?". For this, "max_cap_value,max_fanout" refer to 3. and "driving_cell" has the same function as "set_input_transition". You can read the DC "man command_name" log to understand it.

 

[sakthikumaran87]

Hi yx.yang

First of all my sincere thanks for you for taking pains in replying to my post!

i feel that i am getting some light to my queries.

Coming to your answer, i have got the following doubts:

"for chip inputs: use set_input_transition and set_input_delay to constraint them.
3.2): for chip outputs: use set_max_transiton/set_output_delay/set_output_load to constraint them.
"

What are factors that make us choose a particular value for these constraints. For ex: how can i found what is the set_input_transition value for my chip input.


Thanks in Advance.
SK

- - - Updated - - -

Hi yx.yang

First of all my sincere thanks for you for taking pains in replying to my post!

i feel that i am getting some light to my queries.

Coming to your answer, i have got the following doubts:

"for chip inputs: use set_input_transition and set_input_delay to constraint them.
3.2): for chip outputs: use set_max_transiton/set_output_delay/set_output_load to constraint them.
"

What are factors that make us choose a particular value for these constraints. For ex: how can i found what is the set_input_transition value for my chip input.


Thanks in Advance.
SK

 

[yx.yang]

Hi, sakthikumaran87:
For chip input/ouptut constraint value: set_input_transition and set_input_delay; set_max_transiton/set_output_delay/set_output_load, you can get them from the following two ways:
2.1): The protocal itself defined the input/ouptut delay of the source chip and destination chip clearly. For example: the PCI specification defined this well. So all the chip will meet the timing spec and when they connected up to make a system, there will be no problem.
2.2): The external chip, which you chip will connected to, must have input/output delay specification in its document. You can get these values from doc of the chip you will connected to. Such as DDR memory.

And if you are the pionerr in this area, you chip need give these parameters in your documnet to make others can connect with your chip successfully.

 

[sakthikumaran87]

Thanks will have a look on it.