demod
Newbie level 2
qpsk by vhdl
Dear friends,
I am implementing a digital QPSK demodulator (Data rate is: 42.4515 MBps) with VHDL for realizing on FPGA. For this, I have developed the sub modules such as:
(1- ) 16 bit Edge sensitive Phase-Frequency Detector (PFD) with up/down counter
(2- ) 32 bit Numerically Controlled Oscillator (NCO) with 9 bit outputs for Sin/Cos generation at a scaling factor of 255 and reference clock is 125MHz .
(3- ) FIR filters (In phase and Quad phase) with pass band frequency at 23MHz, stop band frequency at 30MHz and sampling frequency at 250 MHz. Sampling factor is 512.
Input is 16 bit, Coefficient is 13 bit and output is 29 bits.
(4- ) Loop filter for second order PLL with the tracking range of +- 400 KHz, critical damping at (0.707), Scaling factor for present input is 1 and for previous input is -0.09. Input is 29 bit, output is 32 bit.
(5-) A simple adder of FIR_I and FIR_Q contents
(6-) Integration of all these blocks with an additional clock gen block.
I have simulated all the blocks individually before integration and I got the expected outputs. But, after integration, the results are not coming properly. My output signal’s frequency is not exactly tracking with the input frequency. It is coming as 2-3 times lower than the expected frequency. Once even if it acquired the lock, it is not holding. What might be the problem in integration?
I got several doubts as follows:
(1) What is the correct clock I have to give for an Up/down counter i.e., is it the data rate or is the same reference clock given for NCO or any other clock? Theoretically, how to analyze which clock has to be given for counting? Similarly for FIRs and loop filter?
(2) Coefficients calculation for FIRs; is it w.r.t. 125MHz or any other high frequency or low frequency clock?
(3) Loop filter design considerations: How to calculate the gain of PFD and NCO and the constraints of loop filter?
(4) How to determine a lock? Is it just a compare or any other logic has to be used?
(5) Is the inputs to PFD is the simple MSB bits of modulator o/p and the NCO o/p? Or whether I have to use all their 9 bits for comparison?
(6) When the up/down counter has to initiate to zero (rest condition, rising event of next mod data or not?)
(7) Whether any Bit sizes of up/down counter, coefficients, loop filter o/p, NCO frequency input and phase offset, etc..is affecting the final o/p?
(8) Whether any default value has to be set initially under the NCO design? If so, which value?
(9) How to check the spectral response of NCO (simulation results from Modelsim as a raw file to Mat lab)?
Kindly guide me to solve the integration problem what I am facing……….
Thanking you,
Demod Proj team.
Dear friends,
I am implementing a digital QPSK demodulator (Data rate is: 42.4515 MBps) with VHDL for realizing on FPGA. For this, I have developed the sub modules such as:
(1- ) 16 bit Edge sensitive Phase-Frequency Detector (PFD) with up/down counter
(2- ) 32 bit Numerically Controlled Oscillator (NCO) with 9 bit outputs for Sin/Cos generation at a scaling factor of 255 and reference clock is 125MHz .
(3- ) FIR filters (In phase and Quad phase) with pass band frequency at 23MHz, stop band frequency at 30MHz and sampling frequency at 250 MHz. Sampling factor is 512.
Input is 16 bit, Coefficient is 13 bit and output is 29 bits.
(4- ) Loop filter for second order PLL with the tracking range of +- 400 KHz, critical damping at (0.707), Scaling factor for present input is 1 and for previous input is -0.09. Input is 29 bit, output is 32 bit.
(5-) A simple adder of FIR_I and FIR_Q contents
(6-) Integration of all these blocks with an additional clock gen block.
I have simulated all the blocks individually before integration and I got the expected outputs. But, after integration, the results are not coming properly. My output signal’s frequency is not exactly tracking with the input frequency. It is coming as 2-3 times lower than the expected frequency. Once even if it acquired the lock, it is not holding. What might be the problem in integration?
I got several doubts as follows:
(1) What is the correct clock I have to give for an Up/down counter i.e., is it the data rate or is the same reference clock given for NCO or any other clock? Theoretically, how to analyze which clock has to be given for counting? Similarly for FIRs and loop filter?
(2) Coefficients calculation for FIRs; is it w.r.t. 125MHz or any other high frequency or low frequency clock?
(3) Loop filter design considerations: How to calculate the gain of PFD and NCO and the constraints of loop filter?
(4) How to determine a lock? Is it just a compare or any other logic has to be used?
(5) Is the inputs to PFD is the simple MSB bits of modulator o/p and the NCO o/p? Or whether I have to use all their 9 bits for comparison?
(6) When the up/down counter has to initiate to zero (rest condition, rising event of next mod data or not?)
(7) Whether any Bit sizes of up/down counter, coefficients, loop filter o/p, NCO frequency input and phase offset, etc..is affecting the final o/p?
(8) Whether any default value has to be set initially under the NCO design? If so, which value?
(9) How to check the spectral response of NCO (simulation results from Modelsim as a raw file to Mat lab)?
Kindly guide me to solve the integration problem what I am facing……….
Thanking you,
Demod Proj team.