ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
cin : in std_logic;
op : in std_logic_vector(1 downto 0);
c : out std_logic_vector(15 downto 0);
cout : out std_logic;
ofl : out std_logic);
end alu;
architecture Behavioral of alu is
component MUXCY_D
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
CI : in STD_ULOGIC;
DI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
component MUXCY_L
port (LO : out STD_ULOGIC;
CI : in STD_ULOGIC;
DI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
component MUXCY
port (O : out STD_ULOGIC;
CI : in STD_ULOGIC;
DI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
signal b_int : std_logic_vector(15 downto 0);
signal cy_int : std_logic_vector(15 downto 0);
signal cy_int_14 : std_logic;
signal cin_int : std_logic;
begin
cin_int <= op(1) and cin;
b_int <= a xor b xor (op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0)&op(0));
MUXCY_L_0 : MUXCY_L port map ( cy_int(0) , cin_int , a(0) , b_int(0));
MUXCY_L_1 : MUXCY_L port map ( cy_int(1) , cy_int(0) , a(1) , b_int(1));
MUXCY_L_2 : MUXCY_L port map ( cy_int(2) , cy_int(1) , a(2) , b_int(2));
MUXCY_L_3 : MUXCY_L port map ( cy_int(3) , cy_int(2) , a(3) , b_int(3));
MUXCY_L_4 : MUXCY_L port map ( cy_int(4) , cy_int(3) , a(4) , b_int(4));
MUXCY_L_5 : MUXCY_L port map ( cy_int(5) , cy_int(4) , a(5) , b_int(5));
MUXCY_L_6 : MUXCY_L port map ( cy_int(6) , cy_int(5) , a(6) , b_int(6));
MUXCY_L_7 : MUXCY_L port map ( cy_int(7) , cy_int(6) , a(7) , b_int(7));
MUXCY_L_8 : MUXCY_L port map ( cy_int(8) , cy_int(7) , a(8) , b_int(8));
MUXCY_L_9 : MUXCY_L port map ( cy_int(9) , cy_int(8) , a(9) , b_int(9));
MUXCY_L_10 : MUXCY_L port map ( cy_int(10) , cy_int(9) , a(10), b_int(10));
MUXCY_L_11 : MUXCY_L port map ( cy_int(11) , cy_int(10) , a(11), b_int(11));
MUXCY_L_12 : MUXCY_L port map ( cy_int(12) , cy_int(11) , a(12), b_int(12));
MUXCY_L_13 : MUXCY_L port map ( cy_int(13) , cy_int(12) , a(13), b_int(13));
MUXCY_D_14 : MUXCY_D port map (cy_int(14), cy_int_14 ,cy_int(13) , a(14), b_int(14));
MUXCY_15 : MUXCY port map (cy_int(15), cy_int(14), a(15), b_int(15));
c <= (cy_int(14 downto 0) & cin_int) xor b_int;
cout <= cy_int(15);
ofl <= cy_int_14 xor cy_int(15);
end Behavioral;