help regarding fpga implemetation

dear all, i doing my master thesis i am feeling in implementation of dsp block in fpga using serial gigbit Ethernet, plz do suggest any hint regarding this ..

kumar1988 said:

dear all, i doing my master thesis i am feeling in implementation of dsp block in fpga using serial gigbit Ethernet, plz do suggest any hint regarding this ..

Click to expand...

Hy,

I don't quite understand what would you like to do.
You don't know how to implement a DSP block in fpga using serial gigbit Ethernet?
You'd like somebody to tell you how to do it?

If this is a thesis you should ask your teacher to give you more details, or at least you should provide more details.

Thank you,
fpgatime

dear all,
i am working on "Designed and Implementation of dsps(Digital signal Processors) block into (FPGA) field-Programmable Gate Array Using High Speed Gigabit Serial interface”.
this my thesis tittle i am facing problem in making serial interface between fpga and dsp block like filter etc,
2nd question, can i implement fpga directly through coding (vhdl or verilog) or should i need mat lab first and then vhdl or verilog.
thanks for your reply

You could do it directly with coding - but producing a matlab model first will help you decide if your HDL is correct.

TrickyDicky said:

You could do it directly with coding - but producing a matlab model first will help you decide if your HDL is correct.

Click to expand...

This is the way to do it.
First, make a Matlab model, that simulates your design ( components, behavior and any other parameters/variables of interest ).
Try to make a model as accuarate as possible.
After that, take the specifications for the HDL part and describe that part in Verilog or VHDL. If you are planning to verify the HDL code to an advanced level, you should use verilog.

fpgatime

Need help for my master thesis.

Dear user,


Please help me, I am in deep trouble, i choose my master project on FPGA, I want to be designed and implement FIR filter into FPGA using high-speed serial gigabit.

I Have write a code in FPGA but I am unable to implement it onto FPGA board using gigabit serial interface, can anyone help me in this regards.


Br:
Sarwan

Re: Need help for my master thesis.

kumar1988 said:

Dear user,


Please help me, I am in deep trouble, i choose my master project on FPGA, I want to be designed and implement FIR filter into FPGA using high-speed serial gigabit.

I Have write a code in FPGA but I am unable to implement it onto FPGA board using gigabit serial interface, can anyone help me in this regards.


Br:
Sarwan

Click to expand...

I think you have a misunderstanding of the problem. You don't implement FIR filters using a gigabit serial interface. You supply data to or send data from the FPGA via the gigabit serial interface. The FIR filter is a normal FPGA implementation of a FIR, which the FPGA vendor probably already has an IP core that you can use.

Re: Need help for my master thesis.

ads-ee said:

I think you have a misunderstanding of the problem. You don't implement FIR filters using a gigabit serial interface. You supply data to or send data from the FPGA via the gigabit serial interface. The FIR filter is a normal FPGA implementation of a FIR, which the FPGA vendor probably already has an IP core that you can use.

Click to expand...

They probably have a core for gigabit interface, too. Looks like your project is solved.

Re: Need help for my master thesis.

ads-ee said:

I think you have a misunderstanding of the problem. You don't implement FIR filters using a gigabit serial interface. You supply data to or send data from the FPGA via the gigabit serial interface. The FIR filter is a normal FPGA implementation of a FIR, which the FPGA vendor probably already has an IP core that you can use.

Click to expand...

first of all thankyou.

Yes, I feel the same way but how to send data via Gigabit serial interface and how would i implement FIR filter into FPGA.


Thanks a lot

Sounds like your first step is acquiring substantial knowledge in FPGA programming and digital signal processing.

Hi,

It's really confusing.

Gigabit is just an interface to send data from A to B.
You surely don't want to process the pure gigabit signals with your FIR filter. You rather want to process some data that are transmitted using gigabit interface.
But where do the data come from? ADConverter? Continously streaming signal like audio? What data rate?
Or an image of a 3D scanner?
Or something else?

I recommend to focus on one problem, then solve it, then focus on the next problem.

Klaus

Hello kumar,

If you have never used an FPGA, this project would be too complicated for you as a start project.
1. I would go with FvM's reply in #10.
2. Gigabit Ethernet implementation and data transfer. If you are using a Xilinx based FPGA dev board read this https://www.xilinx.com/support/docu..._ethernet_mac/v9_0/pg051-tri-mode-eth-mac.pdf
3. FIR filter can also be implemented using available Xilinx DSP blocks.

Nevertheless a proper project description is still missing. It seems like you just know that 2 components have to be built without knowledge what to do with them.

KlausST said:

Hi,

It's really confusing.

Gigabit is just an interface to send data from A to B.
You surely don't want to process the pure gigabit signals with your FIR filter. You rather want to process some data that are transmitted using gigabit interface.
But where do the data come from? ADConverter? Continously streaming signal like audio? What data rate?
Or an image of a 3D scanner?
Or something else?

I recommend to focus on one problem, then solve it, then focus on the next problem.

Klaus

Click to expand...

What I want is to develop 8 coefficients, FIR filter into FPGA using CDA and MDA method, once FIR filter implemented through FPGA I want FPGA with PC through serial Gigabit interface, and will transfer a distorted voice over it and want to observe behavior of FIR filter and its results, like amplitude, frequency and efficiency etc.

Hope you got what I am trying to do, is this possible, if yes then can you guide me how.

- - - Updated - - -

thanks for your reply, I do have very good knowledge in DSP, average understanding of FPGA, but it doesn't matter now because I have last chance to submit project and I cant change it, What I want is to develop 8 coefficients, FIR filter into FPGA using CDA and MDA method, once FIR filter implemented through FPGA I want FPGA with PC through serial Gigabit interface, and will transfer a distorted voice over it and want to observe behavior of FIR filter and its results, like amplitude, frequency and efficiency etc.

Hope you got what I am trying to do, is this possible, if yes than can you guide me how.

Hi Kumar,
Is serial Gigabit Ethernet a requirement? (I assume you referring to SGMII interface)
Or is it ok to use other interfaces like RGMII or GMII or even 100Mbit RMII/MII?

Is it real-time voices or recorded voices?

When I read what you are going to do I should have used an Ethernet core with UDP or TCP with a AXI4 Stream interface.
It is much easier to send UDP or TCP from a PC than raw Ethernet packets. Especially if you want to do it directly from e.g. Matlab.

Cheers

This is possible, but is not easy as a beginner.
The audio will be packetised over the ethernet, so you will need to learn how to decapsulate the UDP then de-packetise your data. Then pass the data in FIR. And then somehow signal all the data back to the host?

I suggest you start reading. This is probably at least a 6 month project.

Requiring Gigabit ethernet seems arbitrary respectively needless for audio data transport. Technically it's unrelated to FIR filter design, so if it's actually a project objective, it should be separated.

Regarding FIR design, what is MDA and CDA method? I don't recognize it as commonly used technical terms in digital signal processing. Why 8 coefficients?

If it's only an 8-coefficient filter, you could just implement a brute-force approach: 8 multipliers and adders. Otherwise, as previously noted, just use an available core. And if this is voice, why do you need a gigabit data rate? Why not a simple parallel (or SPI) ADC?