[SOLVED] help psl force signal embedded vhdl (compiled, simulated by modelsim 6.5a)

[nicklas_a74]

Hi

I want to use embedded psl into a vhdl testbench and force a signal
to e.g. '0' and then unforce it. How to write psl for this? I compile and
simulate my design using modelsim 6.5a. I have seen different syntax for
this but unsure how to get it to work. I dont want to write commands
in modelsim only embed it into the "normal" testbench .vhdl file

--psl ??? <= force '0';

 

[alsaadawi]

Hi

I want to use embedded psl into a vhdl testbench and force a signal
to e.g. '0' and then unforce it. How to write psl for this? I compile and
simulate my design using modelsim 6.5a. I have seen different syntax for
this but unsure how to get it to work. I dont want to write commands
in modelsim only embed it into the "normal" testbench .vhdl file

--psl ??? <= force '0';

HI
Check the ModelSim reference manual
https://cseweb.ucsd.edu/classes/fa10/cse140L/lab/docs/modelsim_ref.pdf
page 130 "signal spy"

Alsaadawi