help: post-parasitic-extraction simulation

[Robert Qi]

I designed a bandgap and hspice simulation showed that it's output=1.25v.
Then I layed out it and did lvs, passed. Then I extracted netlist including parasitic R and C from the layout with xcalibre, simulated again and found that its output=1.8v (power supply).
Firstly, I thought the parasitic netlist had errors, so I deleted all parasitic R and C, did lvs, passed, and then simulated again, the output was also 1.8v.
Now the extracted netlist is almost the same with schematic generated netlist, except that the extracted netlist contains AD, PD , AS, PS. I am confused. I cannot believe the AD,etc parameters really could cause so much difference on output voltage.
Could anyone tell me whether my bandgap really has prolem, or there was something wrong with the extracted netlist?

 

[sunking]

does the R and diode has extarct rightly? check it.

most question is extarcted netlist

 

[flushrat]

check the extracted triode

 

[selvaraja]

i think there some problem in extraction file ..plz patch or update the pdk..

 

[Robert Qi]

Thank all of you first.
But I check the extracted netlist, and find no problem of R or triode. There is no diode in my ckt.
If any error, I think I would not pass LVS, but I have passed.

My extraction command file comes from my foundry, and I use calibre v9.3.

Unfortunatelly, I haven't found where the problem is.

Dear selvaraja, different-version tool can also cause such problem? Thanks again for you reply.

 

[nxing]

Check the switches for your LVS, that can cause problems, sometime

 

[Robert Qi]

I have found the reason. I deleted the area parameter of BJT, and the bandgap worked!
I think it is my foundry's model that causes problem.
The model is about a fixed emitter bjt, So maybe adding area to it will cause the problem. any idea?
Thank you all, especially Mr. / Ms. flushrat's hint.