Help on verilog code!

[yann_sun]

Hi, all
Why the commands in "always begin end" executed at the time zero?
The following is the brief codes.

...
initial begin 
A <= 0;
# 10 A <= 1;
...
end
...
..
.
always @(negedge A) begin
some commands 
some more
...
end

 

[ciciw]

A is not a clock signal, so it is level triggered, not edge triggered.

 

[poluekt]

Non-blocking assignment A <= 0; bring delta-cycle, this expression equivalently #0 A=0;
Use A=0; instead A <= 0; for solve this problem.

 

[yann_sun]

Using A=0 still fails to solve the problem. There is no discrepancy. Any hint?

 

[dave_59]

If you are using any simulator that support SystemVerilog, if you write your code as

reg A = 0;

The initialization of A is guaranteed to execute before any always or initial block execute.
Alternatively you could make the first assignment to A=1, but then you would have the problem for @(posedge A) if there are any.

 

[tariq786]

Dave welcome to EDABOARD!


Could you answer my post on

https://www.edaboard.com/threads/234194/

Thanks

 

[dave_59]

Sorry, the only thing I can give out for free is advice :|

 

[tariq786]

Thanks Dave.

Where there is a will, there is a way.

 

[yann_sun]

that helps

 

[maizic]

because in verilog any signal default is X, intial begin A =0 end will bring A jump from X to 0, that's mean a negedge tigger

 

[jeet_asic]

It means that "reg" gets executed before any other code/block , irrespective of priorities . but why "reg" gets executed first ?

If you are using any simulator that support SystemVerilog, if you write your code as

reg A = 0;

The initialization of A is guaranteed to execute before any always or initial block execute.
Alternatively you could make the first assignment to A=1, but then you would have the problem for @(posedge A) if there are any.