[SOLVED] HELP on understanding .tcl file.

[karthiga05]

Hi everyone. I need to understand these following 3 lines from my .tcl file. Can someone please explain the bold codes to me? Thanks in advance!

[B]read_netlist /MicroE/microe01/units/AUDIO/HVT/final_hvt.v  -top ml_classifier_chip
read_sdc /MicroE/microe01/units/AUDIO/HVT/final_hvt.sdc


read_vcd -vcd_module top_inst -module ml_classifier_chip /MicroE/microe01/units/AUDIO/HVT/compute.vcd [/B]

# read_vcd -activity_profile -time_window 10000 -simvision -vcd_module top_inst -module ml_classifier_chip /MicroE/microe01/units/AUDIO/HVT/compute.vcd 

# read_vcd -vcd_module ml_classifier_chip -module ml_classifier_chip -start_time 0 -end_time 141606000 /nypdata04/digital/digit_02/projects/Audio/RC/init.vcd

[B]report power > $resultsDir/final_power_hvt.rpt
report gates > $resultsDir/final_gates_hvt.rpt[/B]

 

[poluekt]

I think that script contains mistakes.
I think that read_netlist is user procedure containing command read_verilog -netlist ... Reads in one or more design or library files in Verilog format
(see manual dc_shell> man read_verilog)
read_sdc Reads in a script in Synopsys Design Constraints (SDC) format.
report is user procedure with parameter containing commands report_power, report_hierarchy etc

 

[karthiga05]

for read_sdc. it says 'RTL compiler creates a cost group for each clock defined in the file.' What does cost group mean?

---------- Post added at 11:39 ---------- Previous post was at 11:21 ----------

I think that script contains mistakes.
I think that read_netlist is user procedure containing command read_verilog -netlist ... Reads in one or more design or library files in Verilog format
(see manual dc_shell> man read_verilog)
read_sdc Reads in a script in Synopsys Design Constraints (SDC) format.
report is user procedure with parameter containing commands report_power, report_hierarchy etc

for read_sdc. it says 'RTL compiler creates a cost group for each clock defined in the file.' What does cost group mean?

 

[kbulusu]

in simple terms, you can view cost group as a bucket of all timing paths that meet certain criteria...at the very minimum, a ckt will have flop-flop paths clocked by clk, input 2 output paths, input to clock, clock to output paths...so each of these will be a assigned a name and timing optimization engine will try to meet timing for each of these buckets or cost groups...you can also define your set of paths and assign a name and ask the timing optimization engine to optimize them...

 

[kinchit]

the best way to know the commands is to type man <command name> in your case read_verilog