Help on Stability of the Current-Mode DC-DC?

[newhand]

Hi guys:
Now I need to design a DC-DC converter,switching frequency is 1Mhz,and I have read AI.Pressman's <Switching power supply design> ,and it seems to me that the book focus on the voltage-mode doing a lot of analysis on the voltage mode stability.But what about the current-mode,since the inductor will not contribute a pole to the loop,how to consider the current amp's gain,how to consider the slope compensation versus stability,and since the output pole now is inverse proportional to the loading resistor, so the output pole will vary greatly when loading is changing,this can be a problem to stability?
I couldn't find any books on these issues ,can you help me?And if u are confused as the same as me,maybe we can exchanged ideas and this may help,u can contact with me through the E-mail below.
Best Regards
Jimmy
E-mail:hust_zhangbin(at)163.com

 

[surianova]

hi!

maybe what u can try is to make output become non-dominont pole, for example use Nmos to drive, source of nmos has impedance 1/gm, with changing of impedance at point ,won't cause the dominant pole to shift too much.

 

[Willt]

Hi friend,

Please refer to ~



Will

 

[jluhzw]

Yes, it is more difficult to finde useful information about current mode than voltage mode converter. You can some practical information from the famous companies' datasheets or application notes.And you also can search what you want in the google site.
I don't konw you meaning about current amp' gain.Is the error amplifier gain or the current sensing transconductance?
As far as slope compensatin is consider, you can firstly find some papers to read in the web.Simply, you can consider the duty cycle and the down slope of the inductor current.It is a difficulty for the current mode converter design.
It is right that the changed load can change the pole of the output.So you should design the error amplifier's transconductance and the output resistance and the loop compensation circuits to make sure the loop have enough phase margin in the all conditions ,such as different load, input ,output , output capacitance. It also depends on how you compensate it, on-chip or off-chip.

Added after 20 minutes:

There are two datasheets which is useful for the loop compensation.
Best wishes.

 

[newhand]

Thanks,jluhzw,you have helped me.I think u have provieded 2 good datasheet for us to design current-mode smps.