Help on sizing transistors of differential folded-cascode op

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shaq

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Process: TSMC 0.18µm

Voltage: 1.8v

DC gain: ≥70dB

UGBW: ≥55MHz

Slew Rate output:≥45V/µs

Slew Rate: 40V/µs

Phase Margin:≥60°

The circuit is shown below.
 

Re: Help on sizing transistors of differential folded-cascod

Make hand analysis to give you quick estimation

Start by assuming proper threshould voltages, then write down ranges of bias voltages (Vb1, Vb2,...etc) that keep all transistors in saturation and out of triode.. also satisfy the required voltage swing..

When you do that, you know by that time for almost all transistors the value of Vgs (as well as the assumed Vth), then, you can apply the saturation current forumula (Of course you know it) then you can get approximate values of W/L (you may assume W/L for some transistors if you don't have enough parameters to calculate it)..

Then, put the obtained values in Gain equation and Slew rate calculations to check your values, if OK, go to simulation, if not, change Vb's values (increase or decrease depending on what you got) and so on..

I hope that helps..
Ahmad,
 

    shaq

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this is a diff op, you also need to add cmfb circuit to the op.
 

Re: Help on sizing transistors of differential folded-cascod

Have you considered removing the compensation resistor and instead connecting the caps between folding nodes and output?
 

Re: Help on sizing transistors of differential folded-cascod

2-stage opamp, it is not easy to add cmfb
 

I think that the second stage is not a must. Only the fold cascode is enough to meet your spec. ahmad_abdulghany's guide is useful
 

Re: Help on sizing transistors of differential folded-cascod

pfd001 said:
I think that the second stage is not a must. Only the fold cascode is enough to meet your spec. ahmad_abdulghany's guide is useful
Click to expand...

Hi pfd001,

Do you mean that remove the class A output stage ,R and C ??
 

Re: Help on sizing transistors of differential folded-cascod


the second stage consists of M13 and M14, i think pfd001's meaning is this.
But two stage can provide good cm range out swing Av and CMRR,why not use?
 

Re: Help on sizing transistors of differential folded-cascod

bbqsky said:
2-stage opamp, it is not easy to add cmfb
Click to expand...

why two stage op is not easy to add cmfb? you can just add cmfb on the first stage.
 

Re: Help on sizing transistors of differential folded-cascod

pfd001 said:
I think that the second stage is not a must.
Click to expand...

That depends on the output swing. The Vdd is 1.8V, so any swing above a few tenth of Volts will benefit greatly from 2-stage "linearity enhancement".
 

How can to calculate the pole1 pole2 and zero?

Thanks a lot
 

Re: Help on sizing transistors of differential folded-cascod

I already designed the size of all the transistors and worked in sat. region.

If Vin=Vip=0.9v, the Von and Vop should be 0.9, but I got a 166.8533mV.

But my open loop gain is already 72.485dB, ugbw is 70.642MHz and phase margin is 73.13°. All meet my spec.

Can someone tell me why my Vop and Von are so low?
 

Re: Help on sizing transistors of differential folded-cascod



try resizing M11 & M12 larger
 

    shaq

    Points: 2
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Re: Help on sizing transistors of differential folded-cascod


Thanks, chungming!!!!!

My Von and Vop both are 891.4697mV and open loop gain become 89.791dB, ugbw change to 77.788MHz!!!!!!
 

Re: Help on sizing transistors of differential folded-cascod

What kind of CMFB should I use ?

Plz give me some suggestions.

Thx!!!
 

Re: Help on sizing transistors of differential folded-cascod

how can you simulate the circuit without a common feedback?
choose the feedback depend on you application.
 

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