[SOLVED] Help on decimation filter (to be used for a delta-sigma ADC)

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Hi,

I need help regarding 2's complement coding scheme to be used on the delta sigma modulator output before feeding to the decimator. Following scheme is suggested in some **broken link removed**:
convert 1b'0 to -1 = 1111...11, and 1'b1 to +1 = 0000...01

My query:

In those theses it is stated that that "in order to convert the final decimator o/p from two’s complement form to binary, the MSB bit needs to be complemented"
- How can just complementing the MSB convert from 2's complement to binary form?

WILL BE VERY GRATEFUL IF YOU PLEASE REPLY

Thanks!
JDP.
 

As an example, look at a signed 8-bit value in two's complement format. The range is -128 (binary 10000000) to +127 (binary 01111111).
When they say "binary form" they mean an unsigned value, where the lowest value is zero. This can be done by adding 128 to the signed value.
The range will then move/shift to be 0 (binary 00000000) to 255 (binary 11111111).
This addition by 128 (binary 10000000) is identical to inverting/complementing the highest bit.
To understand that, pick some values and do the addition manually with a paper and a pen.
 
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