Ruritania
Member level 5
inductor layout
Hi,
Is anyone here have any experience on on-chip layout? Please help me out ...
1. Does the inductor layout need substrate contact which ties to ground? Why and Why not?
2. Does the inductor need n-well under it?
3. Does the PGS (Patternedound Shield) need to be tied to ground pad through metals, or just tie it to the substrate?
4. Please refer to the attached pix. It's from an JSSC paper of Hung-Wei Chiu's, publised this year. I'm wondering what's those stuff indicated by(1) and (2)? (the white block under the inductors and capacitors -- (1), and those rectangle shape black blocks--(2))
Thank you.
Ruri
Hi,
Is anyone here have any experience on on-chip layout? Please help me out ...
1. Does the inductor layout need substrate contact which ties to ground? Why and Why not?
2. Does the inductor need n-well under it?
3. Does the PGS (Patternedound Shield) need to be tied to ground pad through metals, or just tie it to the substrate?
4. Please refer to the attached pix. It's from an JSSC paper of Hung-Wei Chiu's, publised this year. I'm wondering what's those stuff indicated by(1) and (2)? (the white block under the inductors and capacitors -- (1), and those rectangle shape black blocks--(2))
Thank you.
Ruri