help!! on ASIC v.2.41 @E|[b]No component

[dd2001]

help!! on ASIC v.2.41

My test_sm.v was successfully syntax and Synthesis checked in ASIC2.41, however, when I press RUN, it wouldn't create netlist for me and generate following error:

@I::"D:\My_Design\test_sm.v"
Verilog syntax check successful!
@E|No component with name test_sm.v to synthesize
@END


I use tutorial.syn come with ASIC 2.41 and have setup time constraint table for test_sm.v.

code as follow:

module test_sm(clock, reset, in_bit, out_bit);
input clock,reset,in_bit;
output out_bit;
reg [2:0] state_reg,next_state;

parameter start_state = 3'b000;
parameter read_1_zero = 3'b001;
parameter read_1_one = 3'b010;
parameter read_2_zero = 3'b011;
parameter read_2_one = 3'b100;

always @ (posedge clock or posedge reset)
if (reset == 1'b1) state_reg <= start_state; else state_reg <= next_state;

always @ (state_reg or in_bit)
case (state_reg)
//start_state:
3'b000:
if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_1_one;
else next_state <= start_state;
//read_1_zero:
3'b001:
if (in_bit == 0) next_state <= read_2_zero; else
if (in_bit == 1) next_state <= read_1_one;
else next_state <= start_state;
//read_2_zero:
3'b011:
if (in_bit == 0) next_state <= read_2_zero; else
if (in_bit == 1) next_state <= read_1_one;
else next_state <= start_state;
//read_1_one:
3'b010:
if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_2_one;
else next_state <= start_state;
//read_2_one:
3'b100:
if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_2_one;
else next_state <= start_state;
default: next_state <= start_state;
endcase
assign out_bit = (((state_reg == read_2_zero) && (in_bit == 0)) || ((state_reg == read_2_one) && (in_bit == 1))) ? 1 :0;
endmodule

 

[bigrice]

it's OK
may be you forgot create a project for this code.

 

[dd2001]

Looks, you are right!

it's OK
may be you forgot create a project for this code.

You may be right, could you show me your project file for this code?


Thanks