Help on All Digital FM Receiver

Hi guys, im trying to follow and implement the specs of an all digital fm receiver presented in this link:

http://www.ie.u-ryukyu.ac.jp/~wada/design05/spec_e.html

im still making the PLL and i dont know if im doing the right thing.. the output of my loop filter ( the one after the multiplier) is a wave much like the output of the multiplier. I tried having the input and reference signal to be in phase and 180 out of phase and same frequency but the output of the loop filter is still a wave... Shouldn't the loop filter would not allow the high frequency to pass through? Shouldn't the output be just a DC value?

I really need help. thanks.

The Loop Filter doesn't significantly attenuate high frequencies, but it amplifies low frequencies by 16 times. Maybe that's what you are seeing.

The following Low Pass Filter stage should remove the high frequencies.

Ohh... how do you know that the loop filter amplifies the low frequencies by 16x? If it only amplifies the low frequency, how does the output of the loop filter control the NCO?

thanks for replying.

The 15/16 feedback provides the low-frequency gain.
By inspection of Figure 2, at steady-state: d(t) = c(t) + 15/16 * d(t)
That rearranges into: d(t) = 16 * c(t)
I simulated it in MATLAB just to be sure.

The low frequency signal at d(t) is the information that you are attempting to detect. In Figure 2 you see that d(t) modulates the NCO (to maintain loop lock), and it passes through the Low Pass Filter (to remove the residual high-frequency junk).

How does d(t) modulate the NCO? How does dividing d(t) which again still has high frequency components change the frequency of the NCO? I am confused in that part.

thanks

In Figure 2, the d(t) wire from the Loop Filter to the NCO block modulates the NCO frequency. That wire is the "input" signal in Figure 3. Figure 3 describes the inner workings of the NCO. It's a phase accumulator type frequency synthesizer.

Please clarify "dividing d(t)". I don't see any divider.

in figure 5, the d(t) is connected to an amplifier diagram with a 1/1024 label and then connected to the phase accumulator

Ok, I see the 1/1024 now. Yes, that block reduces the amplitude of d(t), so it contributes to setting the loop gain.

Do things make sense now, or am I still not grasping your question?

How does reducing the amplitude of d(t) ( which is a wave) contribute to the appropriate phase accumulator? If two signals are already 90 degrees out of phase, then there is no need to adjust the accumulator right? So i thought, if i plug in an input and ref signal that is 90 degrees out of phase, d(t) should be equal to zero so that the ref signal will no longer change. But when i simulated it, d(t) does not go to zero. what am i missing?

Added after 1 hours 10 minutes:

echo47 said:

The 15/16 feedback provides the low-frequency gain.
By inspection of Figure 2, at steady-state: d(t) = c(t) + 15/16 * d(t)
That rearranges into: d(t) = 16 * c(t)

Click to expand...

Also, should d(t) = c(t) + 15/16 * d(t) be d(t) = c(t) + 15/16 * d(t-1) ?

thanks

In Figure 2, when in(t) and ref(t) are 90 degrees out of phase, then c(t) and d(t) should have an average value of zero. (If it isn't zero, then something is broken.) You will also see the high-frequency component, but try to ignore it. The important factor is the the signal's average value.

In figure 3, you see "input + OFFSET". That sum controls the NCO's frequency. If you force "input" or d(t) to zero, then the NCO frequency should be close to the center frequency of your FM input signal in(t).

"Also, should d(t) = c(t) + 15/16 * d(t) be d(t) = c(t) + 15/16 * d(t-1) ?"
Yes, but that spoils the algebraic simplification. I simply assumed very low frequency or DC, where d(t) approximately equals d(t-1). I suppose "steady-state" was the wrong word.

so the average of c(t) and d(t) serves as an "input" to the NCO right? but how does division by 1024 yield the average and the appropriate input to the NCO?

thanks.

There is no averaging circuit. The 1/1024 stage simply helps to set the loop gain.

d(t) is the frequency control input to the NCO. This signal contains both high-frequency and low-frequency components. Both components modulate the NCO, but the high-frequency component has relatively little effect on overall system behavior, it simply causes some NCO frequency jitter. The low-frequency component is the important one, because that's what eventually goes through the Low Pass Filter in Figure 2.

ei what if I use another sampling frequency and another carrier frequency for the FM signal, will the design still work?

thanks for the previous reply.. more or less im already getting the idea.. if d(t) is going to be divided by 1024 ( or right bit shift by 10) and if there are 12 bits, then we are only getting the 2 MSB's? am i right? honestly, im confused with the notation <12,-6,t>..

Added after 1 hours 24 minutes:

Also, how does one compute for the 1/1024 stage? i mean, how did the author know that it is 1/1024? is this also for loop stability? so i have to get a transfer function?

If you keep the same ratio between sampling frequency and FM carrier frequency, then the design should continue working without modification. Keep in mind that changing the sample frequency also changes the cutoff frequencies of the filters.

If you change the frequency ratio somewhat, then you'll also need to change the +0.0625 value that sets the NCO center frequency. That value is basically the tuning knob on your FM radio. If you change the frequency ratio dramatically, then you may need to modify the filters, and maybe adjust some of the arithmetic to avoid overflow or underflow. I'm not too sure about those details without studying the whole system.

The <x,x,x> fixed-point notation is confusing!

The 1/1024 stage doesn't throw away bits, it simply changes the assumed position of the decimal point. Notice how I've aligned the decimal points:
I think that's correct, but I'm not 100% sure. Please double-check!

I'm pretty rusty at designing transfer functions for loop stability. Hopefully someone else can answer that question for you!

oh thats ok. you've help alot...

i was able to implement the PLL but since i still dont understand the 1/1024 stage and the fixed point notations, i made some adjustments... at some point the notations do not matter much since the way they are treated in operations are the same. i just thought of them as way of minimizing or maximizing the effects of a certain signal (much like amplify or attenuate for the appropriate loop gain). anyway, my NCO is 256 by 8k ROM so my accumulator only outputs 8 bits instead of 11. i did not care about the notation and just thought of it as having values from 0 to 255.

then for simplicity, i just get the 8 most significant bits of the output of the loop filter (the d(t) in figure2) and used it as an input for the NCO (lets call it A).

I tried varying A by right bit shifting and also tried varying the input frequency. I found out that by right bit shifting once, a more frequencies (more or less centered on the free running frequency of the PLL) were able to be frequency-locked...

This All Digital FM Receiver is based on frequency-locking mechanisms of the PLL right? so the bandwidth of the input signal does somehow depends on A? sorry im kinda new to PLL's ^_^

Added after 2 hours 37 minutes:

i have a smarter question.. how does one determine the lock and capture range of this all digital PLL?

thanks

Ok good! Hopefully your signals resemble the waveforms shown on that web page.

I'm not sure I understand your input bandwidth question. Maybe you meant lock range or capture range? Either way, I'm too rusty to give a good answer!

I implemented most of it in Verilog, but omitted the output Low Pass Filter. Input signal generator not shown here. It runs in ModelSim. (Beware, most synthesis tools don't support the math functions I used to initialize the ROM.)

In the simulation output, you can see how the loop adjusts the NCO until ref(t) "ref" is nominally 90 degrees from in(t) "fmin". The GIF is somewhat crowded, but semi-readable.

I was able to simulate it in Verilogger and i want to make adjustments to lower down the center frequency ( i have to use 50 MHz clock ) and the widest lock range possible. Im trying to use 65536 x 8bit ROM instead of 256 x 8bit ROM for the NCO.. So i have to modify how the output of the loop filter affect the NCO accumulator... any idea on how to modify the loop filter? though i am also thinking of just left bit shifting the output...

btw, i just posted another topic on the lock and capture range of the DPLL.
This is off the topic: how do check for topics/ posts? do you go to recent posts (like what i usually do) or do you go to the threads of general topic like Network, Digital Communications or the one here- PLD, SPLD, GAL, CPLD, FPGA Design

I assume you want to maintain the original 1 MHz input signal frequency.

Maybe you could simply divide the 50 MHz clock by 3 to get about 16.67 MHz. That's close enough to the old 16 MHz so you wouldn't need to modify the filters. You would only need to decrease the NCO offset value from +0.0625 to +0.0600.

If you want to redesign everything for 50 MHz clock, the first step would be to change the NCO offset value from +0.0625 to +0.02. The loop will now lock, but the transient response will be different.

Next, to keep approximately the same lock/capture range as before, you can slow down the Loop Filter by changing the 15/16 feedback to 49/50. Its low-frequency gain will now be 3.125x greater, so you'll probably want to attenuate it somewhere. Watch out for overflow if you are using binary registers. The NCO input will also be 3.125x more sensitive, so you'll want to attenuate it too. Here one way to do it in my Verilog example. I chose integers that divide easily in binary, but the ratios aren't exactly 3.125:
The new transient response is similar to the old 16 MHz design, but not identical. The difference may be due to the shorter time delays around the loop at 50 MHz, but I'm not sure.

To increase the lock range ... well I'm too rusty to suggest the best way!

Changing the sine lookup ROM from 256x8 to 65536x8 is easy. Simply use the upper 16 bits of the NCO accumulator instead of the upper 8 bits. (However, I wouldn't expect to see much performance benefit from using such a big ROM.) My Verilog example has a 1024x8 ROM, so it uses the upper 10 bits.

I don't use "Recent posts". I usually browse the forums that I'm interested in. I also click "View your posts" to see if there's any new activity in the discussions that I've participated in.

actually i want to have a carrier frequency way smaller than 1MHz... so ill just have to lower my sampling frequency...

in your verilog code,

d <= ireg * ref / 128 + d * 15 / 16;


why did you divide it by 128? i also did it but i forgot why..^_^

--> never mind, it's just a matter of scaling...

if i am going to change 15/16, how will it change the cut-off frequency? if say, i want to change it to 255/256. at steady state, it can amplify the signal with 256 right? but it will also lessen the range of low frequencies that it can amplify. am i right?