Help needed on basic Verilog coding--"for looping"

[Renjie]

Hi guys,

I'm trying to test a 5*5 multiplier; and the two inputs are required to cover all possibilities. So I use two for looping like this:

module tb_mult5x5();
reg [4:0] InA=0, InB=0;
wire [9:0] Product;
integer clk,fp;

mult5x5 mult(InA,InB, Product);

initial begin
for(InA=0;InA<=5'b11111;InA=InA+1)begin

for(InB=0;InB<=5'b11111;InB=InB+1)begin

#1; end
end
#5;
$stop;
end

After simulation, I notice the InA was stuck at 0 and InB goes from 0 to 11111 again and again, obviously the processing can't jump out from the second for looping.

Can anyone figure out what's going wrong here?

Thanks!

 

[tariq786]

Dude there is no clock !!!

put the clock like this


initial
clk <= 1'b0;

always
#5 clk = ~clk;


Then try this code.

 

[Alosevskoy]

I think the problem is not in the clk signal... because you dont need it to simulate a pure combinational multiplier...
The loop never stops because the condition is always true. Let's see.... InA = 11110, 11111, 00000, 00001.. and again, and again.... :-D (the same things actual for InB loop)
To solve the infinite looping you need to extend InA and InB with one more bit and send to your multiplier only InA[4:0] and InB[4:0].

Good luck!

 

[tariq786]

You can also debug this in the waveform viewer of the tool that you are simulating with.
If this does not help,let me know

 

[Renjie]

Thank you guys, I solved it!

 

[tariq786]

Can you explain in detail, how did you solve it and what was the exact problem so that we all benefit.

Thanks

 

[Renjie]

sure, just like exactly Alosevskoy pointed out, the InB is 5 bit; however in the for looping, the boundary condition is InB <= 11111, it will always be true. That's why it won't get out of the loop. Simply we just change the bit of InB, then it works.