[SOLVED] Help needed in VHDL FSM sequence detector 0101

Hi, I am developing VHDL code for 0101 sequence detector. When i simulate, i get 0 output no matter what the sequence is. I have used JK flipflop to implement the design. In my code, im calling JK ff through component port-map. JK ff works fine individually but in the top-level module, its output is always zero.
there's some warning when i check behavioral syntax in simulation space.
WARNING:HDLCompiler:89 - "C:/Documents and Settings/FSM_seqdetector_0101/FSM_seqdec_0101.vhd" Line 60: <jkff> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:89 - "C:/Documents and Settings/FSM_seqdetector_0101/FSM_seqdec_0101.vhd" Line 61: <jkff> remains a black-box since it has no binding entity.Completed static elaboration

Any idea where is the problem???

Here my code for reference.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM_seqdec_0101 is
Port ( x : in STD_LOGIC;
clk : in STD_LOGIC;
z : out STD_LOGIC);
end FSM_seqdec_0101;

architecture Behavioral of FSM_seqdec_0101 is

signal sj1,sj2,sk1,sk2:std_logic;
signal so2:std_logic:='0';
signal so1:std_logic:='0';
signal so1q: std_logic:='1';
signal so2q: std_logic:='1';

component JKFF
port(J,K: in std_logic;
q,qb: inout std_logic;
clk:in std_logic);
end component;

begin

sj1<=x and so2;
sk1<=x or so2;
z<=so1 and so2 and x;

sk2<=x;

JKFF1: JKFF port map(j=>sj1,k=>sk1,clk=>clk,q=>so1,qb=>so1q);
JKFF2: JKFF port map(j=>not sk2,k=>sk2,clk=>clk,q=>so2,qb=>so2q);

end Behavioral;


JK ff code:
entity JKFF is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
q : inout STD_LOGIC;
qb : inout STD_LOGIC;
clk : in STD_LOGIC);
end JKFF;

architecture Behavioral of JKFF is

signal qtemp:std_logic;
begin

process(clk)
begin
if(clk'event and clk='1') then
if(j='0' and k='0') then
qtemp<=qtemp;
elsif(j='0' and k='1') then
qtemp<='0';
elsif(j='1' and k='0') then
qtemp<='1';
elsif(j='1' and k='1') then
qtemp<=not qtemp;
end if;
end if;
end process;
q<=qtemp;
qb<=not qtemp;

end Behavioral;

schematic:

i guess jkff is not part of the project and has not being compiles.

Hi,
thanks for the help. I missed to 'add source' for JKFF in design window. Now its working. I had to add one more buffer to get the output.
Here's the VHDL code n test-bench code for anyone required:

VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity FSM_seqdec_0101 is
Port ( x : in STD_LOGIC;
clk : in STD_LOGIC;
z : inout STD_LOGIC);
end FSM_seqdec_0101;

architecture Behavioral of FSM_seqdec_0101 is

signal sj1,sj2,sk1,sk2:std_logic;
signal so2:std_logic:='0';
signal so1:std_logic:='0';
signal so1q: std_logic:='1';
signal so2q: std_logic:='1';
signal ztemp,zbar:std_logic;

component JKFF
port(J,K: in std_logic;
q,qb: inout std_logic;
clk:in std_logic);
end component;

component and3bit
port(a,b,c: in std_logic;
zut std_logic);
end component;

begin

sj1<=x and so2;
sk1<=x or so2;

sk2<=x;
sj2<=not x;

JKFF1: JKFF port map(j=>sj1,k=>sk1,clk=>clk,q=>so1,qb=>so1q);
JKFF2: JKFF port map(j=>sj2,k=>sk2,clk=>clk,q=>so2,qb=>so2q);
and31: and3bit port map(a=>so1,b=>so2,c=>x,z=>ztemp);

JKFF3: JKFF port map(j=>ztemp,k=>not ztemp,clk=>clk,q=>Z,qb=>Zbar); --buffer


end Behavioral;




test bench:
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY FSM_seqdec_0101_tb IS
END FSM_seqdec_0101_tb;

ARCHITECTURE behavior OF FSM_seqdec_0101_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT FSM_seqdec_0101
PORT(
x : IN std_logic;
clk : IN std_logic;
z : inOUT std_logic
);
END COMPONENT;


--Inputs
signal x : std_logic := '0';
signal clk : std_logic := '0';

--Outputs
signal z : std_logic;

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: FSM_seqdec_0101 PORT MAP (
x => x,
clk => clk,
z => z
);

-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;

wait for clk_period*2;
wait for clk_period/2;
-- insert stimulus here
x<='1',
'1' after 10ns,
'1' after 20ns,
'0' after 30ns,
'1' after 40ns,
'0' after 50ns,
'1' after 60ns, --1
'0' after 70ns,
'1' after 80ns, --1
'0' after 90ns,
'1' after 100ns, --1
'0' after 110ns,
'1' after 120ns, --1
'1' after 130ns,
'1' after 140ns,
'0' after 150ns,
'0' after 160ns,
'1' after 170ns,
'0' after 180ns,
'0' after 190ns,
'1' after 200ns,
'0' after 220ns,
'1' after 240ns, --1
'0' after 250ns,
'1' after 260ns; --1



wait;
end process;

END;