something11
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Hi all
i have written verilog-AMS code for adc and symbol for this is automatically generated. i used this symbol and created schematic of testbench when i try to simulate this i am getting an error that I0:is an an instance of undefined model adc.but i have already written the verilog-ams code for ADC and i am using that symbol only.
plzzzzzz help me to solve this issue
i have written verilog-AMS code for adc and symbol for this is automatically generated. i used this symbol and created schematic of testbench when i try to simulate this i am getting an error that I0:is an an instance of undefined model adc.but i have already written the verilog-ams code for ADC and i am using that symbol only.
plzzzzzz help me to solve this issue