sakthikumaran87
Full Member level 3
Help needed in Primetime!!!
i have a doubt for a long time. DC/RTL compiler instantiate a gate with a certain drive strength by keeping DRC constraints in mind. But in PT we are changing the drive strength of the gates to achieve timing. But wat if the change in the drive strength violates DRC/ cause funtionality mismatch to occur due to reduced drive strength. How to check this as PT itself is a sign-off tool?? Any idea??
Thanks in Advance,
SK
i have a doubt for a long time. DC/RTL compiler instantiate a gate with a certain drive strength by keeping DRC constraints in mind. But in PT we are changing the drive strength of the gates to achieve timing. But wat if the change in the drive strength violates DRC/ cause funtionality mismatch to occur due to reduced drive strength. How to check this as PT itself is a sign-off tool?? Any idea??
Thanks in Advance,
SK
Last edited: