help needed in designing a CMOS D Flip Flop

BB11 · Feb 22, 2012

Hello . I wanna design a cmos d flip flop in 130nm tech. Could any one tell me abt the deisgn considerations ? or does any one hav a circuit design for the same ?

nisshith · Feb 22, 2012

schematic for CMOS D Flip flop :
https://www.iis.ee.ethz.ch/~kgf/aries/FIG/fig4.5.gif

BB11 · Feb 22, 2012

nisshith said:
schematic for CMOS D Flip flop :
https://www.iis.ee.ethz.ch/~kgf/aries/FIG/fig4.5.gif

Thanks Nisshith... Could you please tell me more on how to decide with the W+L ratios?

nisshith · Feb 23, 2012

it is a simple circuit as usual Width for PMOS should be approxx two times of the NMOS.

BB11 · Feb 23, 2012

nisshith said:
it is a simple circuit as usual Width for PMOS should be approxx two times of the NMOS.

I am using the following d flip flop . And i don get the expected output voltage between master and slave point as well as the output

nisshith · Feb 23, 2012

use nMOS transistors W=2 , and all pMOS transistors W=5.6
for more info refer 4.A Programmable Digital Filter Architecture - Aries

help needed in designing a CMOS D Flip Flop

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