sanjay said:Project Name : Binary Up/Down counter
Device : Spartan XCS10 4pc84
Frequesncy : 25 Mhz
Tools using : Xilinx ISE Software, Synplify 7.3 ( for synthesis purposes )
Model SIm ( timing simulation )
This is the code.
As you might have observed we delaying the leds on the board after every 1 second.
Now everything is going on fine.. No problem
But when we run it on the development board the LEDS stay permanently On ( its counting but counting toooo fast )
We checked for following :
1.Timing Simulation : Runs perfectly the way it should. Increments or Decrements the LED after 1 second.
2.Checked timing reports. there we saw one thing which is as following
Constraint | Requested | Actual | Logic Levels
--------------------------------------------------------------------------------
TS_CLK = PERIOD TIMEGRP
"CLK" 40 nS HI | 40.000ns | 15.050ns | 4
GH 50.000000 %
--------------------------------------------------------------------------------
OFFSET = OUT 40 nS AFTER
COMP "CLK" | 40.000ns | 9.235ns | 1
--------------------------------------------------------------------------------
OFFSET = IN 40 nS BEFORE
COMP "CLK" | 40.000ns | 15.452ns | 4
--------------------------------------------------------------------------------
Seeing this report during the place and route phase it appears that somehow it instead of 40ns which is wht we require its using its own timing.
Help would be appreciated..if someone can suggest toget the ACTUAL also to 40ns
Thanks
Sanjay
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