help needed for FPGA timing constraint

[cdcll]

I have 2 oscillators connected to the fpga, the freq. of one is much higher than the another, I would like to know how to set the timing constraint for the different requirement in the same peoject, such as Fmax, setup time, hold time etc.

Thanks!

 

[cdcll]

can anyone help me? I use qu@rtus II v3.0.