Help needed about subthreshold circuit design!

Hi,

I am working on the design of some subthreshold circuits based on TSMC 0.18 cmos process. But there is huge difference between the simulation and measured results.

I designed a regulator(power consumption=1uW) based on the subthreshold voltage reference proposed in the paper "A 300 nW, 15 ppm/ C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs". Simulations show that Vout=1.8V@TT 1.6~2V@TT/ff/ss. However, the measured result of all chips is Vout=1.9~2V. I also simulate it with PCM DATA provided by the foundry, and I got the highest Vout=1.85V at worst case.

Another circuit is a low power oscillator(power consumption=1.4uW, f=1.92MHz). The measured clock frequency of most chips is only about 1.5MHz, while post-simulations predict the lowest freq is 1.7MHz at worst case.

Any help will be appreciated!!!

Interesting results... Which corners have you used for simulations (especially for that one you mention as a worst case)?

I have simulated TT FF SS for the regulator and osc with the model in the pdk. I have also simulated TT FF SS FS SF for the osc with a changed model according to the PCM DATA.

Do you have an on chip current reference?
Which oscillator topology have you used?

jkatic said:

Do you have an on chip current reference?
Which oscillator topology have you used?

Click to expand...

I use the oscillator topology presented in this paper.

wangyuestc said:

...But there is huge difference between the simulation and measured results...

Click to expand...

How condifent are you that the spice models are accurate in the sub-threshold region?

You should put this question to your technical contact at TSMC.

I have read your paper, nice work btw. However, I think that resistors are probably the source of your problem. I dont see anywhere in you paper discussion on resistor process variations, This well resistor you used in osc have huge process variation (as 30%), you also use resistors to generate Vctrl and inside LDOs. Did you also simulate resistors over corners and MC? Maybe your models for resistors are bad, you should try to run MC just with resistor models set up to MC (for the rest you take typ) to see wheter they are OK.

jkatic said:

I have read your paper, nice work btw. However, I think that resistors are probably the source of your problem. I dont see anywhere in you paper discussion on resistor process variations, This well resistor you used in osc have huge process variation (as 30%), you also use resistors to generate Vctrl and inside LDOs. Did you also simulate resistors over corners and MC? Maybe your models for resistors are bad, you should try to run MC just with resistor models set up to MC (for the rest you take typ) to see wheter they are OK.

Click to expand...

Hi Jkatic,
I will try the MC. But there is no resistors in the regulator, the resistors in the schematic is diode connected pmos working in subthreshold. And we have measured about 20 chips, the Vout of the regulator(which is supposed to be 1.8V) is around 1.9~2V for all chips. That is weird.

Yes, it is weird. I am worried because my next chip will mostly work in subtreshold and it is similar technology, UMC 180nm. Obviously, you have to be very careful with the models and during MC/corner simulations. Please post here if you discover what was the problem.

Since the circuit is such a low power circuit, it would have many high impedance nodes.

Are you by any chance bringing out any high impedance nodes to a pin? Then the pad leakage and board leakage would screw up the that node by causing a voltage drop.

nitishn5 said:

Since the circuit is such a low power circuit, it would have many high impedance nodes.

Are you by any chance bringing out any high impedance nodes to a pin? Then the pad leakage and board leakage would screw up the that node by causing a voltage drop.

Click to expand...

Hi nitishn,

In fact, the measured output voltage of the regulator is higher than the simulated value. For the oscillator, there is no high impedance node connected to a pin.