hung_wai_ming(at)hotmail.com said:
I have faced similar problems several years ago.
My approach for doing PLL is like this
(1) Read papers from IEEe for knowing basics and some existing achitectures
(2) Choose the best papers from IEEe. Here are some list of authurs who I think
the best in PLL design
F.M. Gardner " charge-pump Phase-Locked Loops"
I.A. Young "A PLL clock generator with 5 to 110MHz of lock range of microprocessors"
J.C. Maneatis, all papers from him are good
JaeHa Kim, all papers from him are good
A. Maxim, all papers from him are practical
(3) Develop system modesl in EXCeL to calculate open loop/close loop response.
Some may use MatLxb, I prefer EXCel as you can type equations and understand more when you play around
(4) Choose one paper to do your design