Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help need in explaning DC Command!

Status
Not open for further replies.

GoodMan

Full Member level 2
Full Member level 2
Joined
Sep 30, 2002
Messages
125
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
646
write_sdf brackets

Hi All.

Who can help?
Please explain this line command :
write_sdf -version 2.1 -context verilog asic_top_21.sdf.
the parameter (-context verilog) has any function

regards,.
 

Re: Help! About DC Command!

without this switch the bus names in your sdf do not match your netlist and this may cause problems in simulations. if you have a verilog netlist its always better to specify "write_sdf -context verilog mysdf.sdf" so design compiler uses proper brackets[] for bus delimiters of your sdf. without this switch a 5-bit bus may appear in your sdf as busx4:0x but with -context this bus shows up as bus[4:0]
 

Re: Help! About DC Command!

I see!
have a nice day !
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top