if u want to use vhdl to describe a static ram for a fpga, you could explicitly instantiate the fpga's ram primitive, like blockRAM in Xiline.
if you want to use vhdl to describe a static ram for any type of fpga that use its primitves, I think you have problem doing it in a single description. Every synthesizer will infer SRAM in a bit different manner. If you don't care the to optimise the use of fpga's primitive, you could always write a SRAM description in VHDL and let the synthesizer to implement it using LUTs, however, it is not recommended for large SRAM size as it consumes too much LUTs that would be used for other uses.
ntxp