finefunny
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Help,about Synplify
Hi,I design a FPGA project. When I synthesis the verilog files using Synplif7.2,I select the option "write to netlist",I get a result,save it. And I synthesis the verilog files again ,but do not select the option "write to netlist',I get another result. To my surprise ,the resource usage of the two results is quite different. Why?I do not know.
Hi,I design a FPGA project. When I synthesis the verilog files using Synplif7.2,I select the option "write to netlist",I get a result,save it. And I synthesis the verilog files again ,but do not select the option "write to netlist',I get another result. To my surprise ,the resource usage of the two results is quite different. Why?I do not know.