Help me with Verilog synthesis in Synplify 7.2.1

[finefunny]

Help,about Synplify

Hi,I design a FPGA project. When I synthesis the verilog files using Synplif7.2,I select the option "write to netlist",I get a result,save it. And I synthesis the verilog files again ,but do not select the option "write to netlist',I get another result. To my surprise ,the resource usage of the two results is quite different. Why?I do not know.

 

[ye.hui]

Re: Help,about Synplify

i guess the reason is the synthesis algorithm of the software if you did not change any other options and constraints. you can build a new project which is the same as the previous one, just the option "write to netlist" is defferent, and observe the results. or you can use a higher version software.