help me with this error message

hdlparsers:709

when i try to check the syantax of the code i get this error message ..plz help me resole it ..i am using xilix 7.1i and am working on vhdl

Xstortability/export/Port_Main.h:127:1.13.276.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com

is not an entity name

hari_lhr said:

when i try to check the syantax of the code i get this error message ..plz help me resole it ..i am using xilix 7.1i and am working on vhdl

Click to expand...

Unless you post your code (or atleast the portion that causes this error) - I'm afraid not many cna help.

Xstortability/export/Port_Main.h:127:1.13.276.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at h**p://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at h**p://support.xilinx.com

Click to expand...

Have you considered the above suggestion? Even they will ask for a testcase

Regards
Ajeetha, CVC
www.noveldv.com

error:hdlparsers:709

this is the code which is generating this error..even the xilinx support quotes the error to be known issue ..plz suggest

library IEEE;
use IEEE.std_logic_1164.all;

entity transmitter is
port (
din: in bit;
clk: in bit;
pout: out bit
);
end transmitter;

architecture main of transmitter is

component divide is
port(clkin:in bit;clkoutut bit);
end component;

component parellelizer is
port(din,clk: in bit; s1,s0: out bit );
end component;

component txpll is
port(s1,s0,clk:in bit;poutut bit);
end component;

for all : divide use entity work.divideby2;
for all : parellelizer use entity work.parellel;
for all : txpll use entity work.tx;

signal clkby2,s1,s0,p:bit;
begin
div : divide port map (clk,clkby2);
parellel : parellelizer port map (din,clk,s1,s0);
tx_pll : txpll port map (s1,s0,clkby2,pout);
end main;

is not an entity name xilinx

hari_lhr said:

this is the code which is generating this error..even the xilinx support quotes the error to be known issue ..plz suggest

Click to expand...

Did you run it rhough Modelsim or any other simulator before moving to Xilinx? Usually simulators are better in flagging errors early on.

In your code I found few issues/suggestions:

Code:

library IEEE;
use IEEE.std_logic_1164.all;

entity transmitter is
    port (
        din: in bit;
        clk: in bit;
        pout: out bit
    );
end transmitter;

Click to expand...

You use std_logic_1164 package but use BIT type - why? Usually in industry std_logic is more prominent in use. This is not the real issue in this case though.

Code:

architecture main of transmitter is

component divide is
port(clkin:in bit;clkout:out bit);
end component;

component parellelizer is
port(din,clk: in bit; s1,s0: out  bit );
end component;

component txpll is
port(s1,s0,clk:in bit;pout:out bit);
end component;

for all : divide use entity work.divideby2;
for all : parellelizer use entity work.parellel;
for all : txpll use entity work.tx;

Click to expand...

Your component name is divide, but you are asking it to use work.divideby2 and so on for other blocks as well.


This I believe is the core issue, fix this. If I may comment - I sense that you are early starter in VHDL, I'm currently building my team and see similar issues/mistakes they make. They are all smart guys, fresh out of M.tech/B.E. I believe the core problem is that there is no "paper design", you started off "typing/coding" - identify what will be your sub-blocks, names, data types etc. Only then you should start coding.

Good Luck
Ajeetha, CVC
www.noveldv.com

xilinx hdlparsers:709

Ya i am a starter ..in VHDl ..but have quite an amount of confidence in the subject though.


I had first created .vhd files using xilinx and had sumulated it with ..ISE simulator, Modelsim, and Sonata too..there was no problem initially

But the problem arised only after i had uninstalled the XIlinx software( evalutaion pack valid for 60 days) and then reinstalled it.

Now I get this particular error....i am not sure why....

I had done most of the paper work myself..plz help me out


The error messages arised

xst is not an entity name

this is tool related problem and not code related
u can verify this by running a different code in ur tool
and moreover i don't think this error message will make xilinx nonfunctional. it continues to work right??
pls let us know the outcome

regards
srinivas

hdlparsers 709

As far as the entity names are concerned.ie..divide instead of divideby2..because i have already defined entities divideby2..etc..in other modules..

Added after 29 minutes:

rsrinivas said:

this is tool related problem and not code related
u can verify this by running a different code in ur tool
and moreover i don't think this error message will make xilinx nonfunctional. it continues to work right??
pls let us know the outcome

regards
srinivas

Click to expand...

ya the other codes are working i fin the problem only with this code..i think the problem is with the sequesnce or ordering or statements..plz comment

ise generate test bench is not an entity name

hari_lhr said:

As far as the entity names are concerned.ie..divide instead of divideby2..because i have already defined entities divideby2..etc..in other modules..

Click to expand...

Then why do you declare "component" named "divider"? make it divideby2 only. Agreed it is a tool bug - you have 2 options - run behind Xilinx to fix the tool (you may finish successfully after 1+ year) - or clean up your code.

If I were you, I will try and fix the code and get going.

As a side note:

Did you consider running a Lint tool say leda/Spyglass? I don't believe free versions are around, but if you belong to a reputed institute, EDA vendors may give you. I can help you with Leda if you want, send me an email at cvc.training <> gmail.com if interested.

Good Luck
Ajeetha, CVC
www.noveldv.com

port_main.h:127:1.13.276.1

ya i changed the code ..used teh appropriate names ..but of no use ..still the same result

portability/export/port_main.h

hari_lhr said:

ya i changed the code ..used teh appropriate names ..but of no use ..still the same result

Click to expand...

You need to show/isolate the source of error in your code. If you can reduce a testcase, send it to me via email at cvc.training <> gmail.com. No promises to look at it right away but maybe by today evening I can see/review

Good Luck
Ajeetha, CVC
www.noveldv.com

not an entity name

aji_vlsi said:

hari_lhr said:

ya i changed the code ..used teh appropriate names ..but of no use ..still the same result

Click to expand...

You need to show/isolate the source of error in your code. If you can reduce a testcase, send it to me via email at cvc.training <> gmail.com. No promises to look at it right away but maybe by today evening I can see/review

Good Luck
Ajeetha, CVC
www.noveldv.com

Click to expand...

Thanks for the concern...
I had changed the component names accordingly throughout the code (for all modules) and i dont get the error <application had encountered....>
but now when I try to get the testbench waveform for the code which i gave earlier i get error..

Line 49. divideby2 is not an entity name
ERROR:HDLParsers:709 - "d:/final/transmitter.vhd" Line 50. parellel is not an entity name
ERROR:HDLParsers:709 - "d:/final/transmitter.vhd" Line 51. tx is not an entity name

Added after 3 minutes:

Ajeetha ..plz let me know what u want me to send?