Help me with solution to latch-up in Xilinx CPLD

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vaf20

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Solution to latch-up

hi all
i use following xilinx CPLD XC9500
9572+95218+95288
what can i do for lath up immunity in my board?
tnx in advance
 

Solution to latch-up

what's your meaning?
 

Re: Solution to latch-up

Hello,

If you want remove the latch up phenomena, you must be sure that the signal on the component entry is never over the component voltage specifications.

If you cannot guarantee this condition then you must force the entry current to be lower than the current that starts the parasitic thyristor.

Hope this help you.

Telga
 

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