i need to match about 15 Mos transistors all with the same N(W2/L)
with one device the same N and (W1/L) where width stripe W2 is sligtly less than W1, (mirror),
The best matching is reached when all transistors have the same size.
Remember to construct a common centroid structure, put all transistors in the same direction and add dummy transistors so that all tranasistors see the same surrounding. If you can divide your basic sructure into say, 4 substructures, and make a common centroid superstructure with your basis one, this would even increase the matching.
and i think your words are not completely right as matching doesnot come only from the fact of large no. of fingers as we need common centeroied in addation to eliminate the effect of the process gradient .
Humungus
The best matching is reached when all transistors have the same size.
Put the reference transistor in the middle, then all transistors should have same size and orientation (don't flip source and drain!), finally add dummies (1 or 2) on each side.
And no metal on top of them!
If your chip has some high consumption block (high temp), they should be at an equal distance: don't put his temperature source on the left or on the right of your mirrors.
Don't think that you will do better than the data specified by your foundry, they already carrefully matched the transistors before to measure the matching data.
Put the reference transistor in the middle, then all transistors should have same size and orientation (don't flip source and drain!), finally add dummies (1 or 2) on each side.
And no metal on top of them!
If your chip has some high consumption block (high temp), they should be at an equal distance: don't put his temperature source on the left or on the right of your mirrors.
What is your reference? W1 or W2?
Is it possible to have real value of N W1 W2 and L?
It is important to determine row and column to approch a square.
Don't forget substrate tie. Never enough.
Do a unit cell that you can flat easily to replace W2 by W1 where you have to.
I will be interested to help you but I need value.
Also to reduce the gate resistance and therefore noise, connect the gate-poly fingers (forming a mesh) on both sides of the drain/source. (See Razavi's analog design book)
Try the book by Saint/Saint on IC layout Basics
or Alan Hasting's book on 'The Art of Analog Layout'