Help me with FPGA/ADC Clock Generation

[Fish4Fun]

FPGA Clock Generation

I am working on an FPGA based DSO project. I would like some input on the FPGA/ADC clock. The project utilizes 2 ADCs capable of up to 250MSPS (Maxim 1121s) and I plan on using a Xilinx Spartan FPGA. For acquisition there needs to be several timebases. These include: 10Mhz, 25Mhz, 50Mhz, 100Mhz, 125Mhz, 150Mhz, 175Mhz & 200Mhz. In addition, the clocks beginning with 100Mhz need a complementary output for interleaving the two ADCs.

I have considered solutions like the ICS511 and the MC12429, but was curious if it would be worth considering a PLL synthesis within the FPGA, or if anyone had any suggestions for a PLL frequency synthesizer chip other than the two mentioned.

Thanks in advance for any input.

 

[yeewang]

FPGA Clock Generation

it's positive to double the frequency inside the FPGA with it's DLL/DCM technology.
but for freq up to 150/200 MHz, as you need, the quality of output clock from I/O pin may be a problem. You'd better try and measure them with a high-resoluation oscilloscope first.

 

[echo47]

FPGA Clock Generation

If you mean Spartan 3, you could use one fixed clock input (such as 50MHz) and four DCMs to generate 125MHz, 150MHz, 175MHz, and 200MHz. Then use some flip-flops to generate the lower frequencies. It's a pity that we can't change the DCM frequency ratio at run-time.

Beware, the DCM adds jitter (see the data sheet). If that's unacceptable to your project, then you'll need several crystal oscillators, or an external clock generator.

 

[Fish4Fun]

FPGA Clock Generation

Echo47, Yeewang,

Thank you both for your input. Jitter is a concern particularly in the upper frequencies. The ADCs have a clock output that can be used to drive the FPGA so I will go with something like the MC12429 directly to the ADCs.

If anyone is familiar with a clock multiplier/PLL with a wide frequency range, low jitter and fairly high fundmental frequency accuracy; please share your input. LVDS output would be a plus.

Again, Thanks in advance.

 

[dddhacker]

Re: FPGA Clock Generation

hello

you can go the Integrated Circuit Systems, Inc. web site. They many diffrent types of clock managers.

**broken link removed**