moharaza
Junior Member level 3
dsp_48
hi,
I need some urgent help, I am trying to design a modular exponential unit for my project which is in deep crisis.
I have designed one, which is not working as expected when it is downloaded on the board. But, The simulation is giving perfect result.
i am not getting any errors, just few warnings--
something like--
"cannot use dsp_48 technology"
please take a look and help me out if possible.
notes--
1.I am using XUPV2P board.
2.post contains 2 verilog files
3.interleavedMultiplier unit is working fine when it is downloaded on the board.
4. I am getting "out=0" from the board when i download ModExp.v
Maruf
hi,
I need some urgent help, I am trying to design a modular exponential unit for my project which is in deep crisis.
I have designed one, which is not working as expected when it is downloaded on the board. But, The simulation is giving perfect result.
i am not getting any errors, just few warnings--
something like--
"cannot use dsp_48 technology"
please take a look and help me out if possible.
notes--
1.I am using XUPV2P board.
2.post contains 2 verilog files
3.interleavedMultiplier unit is working fine when it is downloaded on the board.
4. I am getting "out=0" from the board when i download ModExp.v
Maruf
Code:
//Exponential calculator
`timescale 1ns / 1ps
/*
for i=bits;i>0;i--
{
if(e[i]==1)result=(result*base)%M;
result=(result*result)%M;
}
*/
module ModExp(clk,reset,start,base,e,M,out,done);
parameter bits=3,Count_Max=3'd4,Count_bits=2;
input clk;
input reset;
input start;
input [bits:0]base;
input [bits:0]e;
input [bits:0]M;
output reg [bits:0]out;
output reg done=0;
parameter IDLE=3'b000, COUNTER = 3'b001, CHECK_FOR_ONE = 3'b010, SQUARE=3'b011, MULT_ONE=3'b100,MULT_TWO=3'b101,BUFFER_A=3'b110,BUFFER_B=3'b111;
reg [bits:0]temp;
reg flag;
reg [2:0]state=0;
reg [Count_bits:0]count;
/*-------------------------Interleaved Multiplier Declaration-------------*/
reg [bits:0]opA=0;
reg [bits:0]opB=0;
reg [bits:0]Mod;
wire doneM;
wire [bits:0]result;
InterleavedMult ah(clk,reset,start,opA,opB,Mod,result,doneM);
reg [bits:0]tempBase=0;
reg [bits:0]tempE=0;
reg [bits:0]tempM=0;
reg tempDone=0;
reg control;
always @(posedge clk)
if((tempBase !=base)||(tempE !=e)||(tempM !=M)||(tempDone!=done))
begin
if(flag)flag=~done;
else flag=1'b1;
tempBase<=base;
tempE<=e;
tempM<=M;
if(done) tempDone<=done;
else tempDone<=0;
end
always @(posedge clk)
if(reset)
state<=IDLE;
else if(start && flag)
case(state)
IDLE:
begin
control<=0;
state<=CHECK_FOR_ONE;
count=Count_Max;
temp=1;
out=0;
end
CHECK_FOR_ONE:
begin
if(e[count-1])
begin
if((opA!=base) || (opB!=temp))
begin
opA=base;
opB=temp;
Mod=M;
control<=0;
state<=MULT_ONE;
end
else state<=SQUARE;
end
else
state<=SQUARE;
end
MULT_ONE:
begin
if(doneM && control)
begin
temp=result;
control<=0;
state<=SQUARE;
end
if(!doneM)
control<=1;
end
SQUARE:
begin
if(count!=1)
begin
if(((opA!=temp) || (opB!=temp)) && (temp>1))
begin
opA=temp;
opB=temp;
Mod=M;
control<=0;
state<=MULT_TWO;
end
else
begin
count=count-1;
done=0;
state<=CHECK_FOR_ONE;
end
end
else
begin
out=temp;
done=1'b1;
state<=IDLE;
end
end
MULT_TWO:
begin
if(doneM && control)
begin
temp=result;
control<=0;
count=count-1;
done=0;
state<=CHECK_FOR_ONE;
end
if(!doneM)control<=1;
end
default:state<=IDLE;
endcase
endmodule
/////////////////////////////////////////////////////// Multiplier///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module InterleavedMult(clk, reset, start, opA, opB, M, out, done);
parameter bits=3,Count_Max=3'd4,Count_bits=2;
input clk;
input reset;
input start;
input [bits:0]opA;
input [bits:0]opB;
input [bits:0]M;
output reg [bits:0]out;
output reg done=0;
parameter IDLE=2'b00, COUNTER = 2'b01, CHECK_FOR_ONE = 2'b10, CHECK_FOR_GRT_M=2'b11;
reg [bits+2:0]temp;
reg flag;
reg [1:0]state;
reg [Count_bits:0]count;
reg [bits:0]tempOpA=0;
reg [bits:0]tempOpB=0;
reg [bits:0]tempM=0;
reg [bits+1:0]temp_M_2=9'd0;
reg tempDone=1'b0;
always @(posedge clk)
if((tempOpA!=opA) || (tempOpB!=opB) || (tempM!=M)||(tempDone!=done))
begin
if(flag)flag=~done;
else flag=1'b1;
tempOpA<=opA;
tempOpB<=opB;
tempM<=M;
if(done)
tempDone<=done;
else tempDone<=0;
end
always @ (posedge clk)
begin
if(reset)
state<=IDLE;
else if(start && flag)
case(state)
IDLE:
begin
temp=0;
count=Count_Max;
state<=COUNTER;
end
COUNTER:
begin
if(count>0)
begin
temp={temp[bits+1:0],1'b0};
state<=CHECK_FOR_ONE;
end
else
begin
done=1'b1;
out=temp;
state<=IDLE;
end
end
CHECK_FOR_ONE:
begin
if(opA[count-1])
temp=temp+opB;
done=0;
temp_M_2={M[bits:0],1'b0};
state<=CHECK_FOR_GRT_M;
end
CHECK_FOR_GRT_M:
begin
if(temp>=temp_M_2)
temp=temp-temp_M_2;
else if (temp>=M)
temp=temp-M;
count=count-1;
state<=COUNTER;
end
default:state<=IDLE;
endcase
end
endmodule