help me with a synthesis concept

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microe_victor

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" For state machine, combinational logic for computing the next state should be in its own process or always block, separate from the state registers."

what does that mean, please explain it and better with some examples,
thank you very much
 

This is an example I got from here:
**broken link removed**

=== The definition of the state variables.
===
reg [1:0] state;
reg [1:0] nextstate;
parameter S0 = 2’b00;
parameter S1 = 2’b01;
parameter S2 = 2’b10;

=== This process contains only state registers.
===
// State Register
always @(posedge clk or posedge reset)
if (reset) state <= S0;
else state <= nextstate;

=== This process contains only the combinational logic for computing the next state.
===
// Next State Logic
always @(state)
case (state)
S0: nextstate <= S1;
S1: nextstate <= S2;
S2: nextstate <= S0;
default: nextstate <= S0;
endcase
 
In writing the code for any fsm , u can devide it into 2 or 3 process (or always) blocks.
any fsm consists of,
1)registers which holds the present state.(sequential)
2)combinational logic to generate the next state logic (combinational)
3)combinational logic to generate the output.(combinational)

Each of them can be written in a seperate block. You can combine the output logic and sequential logic into the same process block but not the next state combinational logic . it is bcoz the next state depends on the present state and u should provide this information by the next clock edge.
 

As in desigining of FSM we shold not mix the Seq. and Combinational logic ,otherwise unwanted Latch would be inferred.

Anmol
 

Make a state machine independent of inferred signal. Infer signals from separate procedural statements. This will solve lot of design issue and debugging will be more easy.
Sumit
 

if i am rgt ....combinational logic should be written out of the process..where u only specify present state and next state.....correct me if i am wrong.......
 

p_shinde said:
if i am rgt ....combinational logic should be written out of the process..where u only specify present state and next state.....correct me if i am wrong.......
Click to expand...

verilog or VHDL?

combo logic can be written in always with all parameters in sensitivity list
Shiv
 

in fact, you'd rather use control signals as condition to control the state transition. And write the combinational logic and sequential logic code in one always block, then you are not afraid that you omit the sensitive signals
 

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