Help me with a multiplexer design error in Cypress 6

help multiplexer

hi all, i am beginner in vhdl

please i need help , i want design a multiplexer 12 inputs and 9 output
in a gal22v10. but in cypress war 6 show this message:MUL.VHD (line 13, col 24): (E607) Choice type 'std_logic_vector(1 to 11)' doesn't match case type 'std_logic_vector(11 downto 0)'.

here is my program

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mul IS PORT (
ent: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
sal: OUT STD_LOGIC_VECTOR (1 TO 9));
END mul;

ARCHITECTURE Behavioral OF mul IS
BEGIN
PROCESS(ent)
BEGIN
CASE ent IS
when "10000010100" => sal <= "111100011";
when "10000010111" => sal <= "111100011";
when "10000010110" => sal <= "110101100";
when "10000010101" => sal <= "110101010";
when "10000010000" => sal <= "110000110";
when "10000010001" => sal <= "101010101";
when "10000010010" => sal <= "101010101";
when "10000010011" => sal <= "101010101";
....................
when others => sal <= "000000000";


END CASE;
END PROCESS;
END Behavioral;

Re: help multiplexer

ent has been defined as 12 bit total
-> ent: IN STD_LOGIC_VECTOR (11 DOWNTO 0);

So you should write when statements like below

when "010000010100" => sal <= "111100011";
when "010000010111" => sal <= "111100011";
^
...
...